Low Temperature Stacked Transistor Fabrication
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Solution Overview
Problem
Current methods for fabricating stacked MOS transistors require high-temperature processing, which can lead to failures and degradation due to electromigration or dopant redistribution, limiting transistor density and compatibility with existing CMOS process flows.
Innovation Solution
A method for forming stacked low temperature transistors involves depositing an inter-layer dielectric and a semiconductor layer on a bulk semiconductor substrate, followed by the formation of gate structures and source/drain regions, with a metal layer deposited over the transistors and annealed at a low temperature to induce reactions, reducing thermal budget and preventing degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-temperature processing is used to form stacked MOS transistors, then transistor density is increased, but circuit degradation occurs due to electromigration or dopant redistribution
Solution Approach 1:
The fabrication process is divided into two distinct stages: first, the underlying IC devices are formed using conventional high-temperature processes; second, the stacked transistor layer is formed using low-temperature processes. This segmentation allows each stage to operate under optimal conditions without interfering with the other, resolving the contradiction between achieving high transistor density and maintaining circuit integrity.
Solution Approach 2:
The patent changes the temperature parameter from high-temperature processing (>900°C) to low-temperature processing (<450°C) for forming the stacked transistor layer. This parameter change enables increased transistor density while preventing thermal damage to underlying circuitry, directly resolving the technical contradiction.
2Manufacturing precision
If high-temperature annealing is used to recrystallize amorphous silicon, then source/drain regions are properly formed, but existing circuitry degrades due to thermal damage
Solution Approach 1:
The annealing temperature parameter is reduced from conventional high temperatures (>900°C) to low temperatures (<450°C). This parameter change enables source/drain region formation through alternative mechanisms that do not rely on high-temperature recrystallization, thereby maintaining manufacturing precision while eliminating thermal damage to underlying circuitry.
Solution Approach 2:
The patent replaces thermal recrystallization mechanisms with low-temperature deposition and in-situ crystallization methods. This substitution eliminates the need for high-temperature thermal processing while achieving equivalent or superior source/drain region quality, resolving the contradiction between manufacturing precision and avoiding thermal damage.
3Reliability
If conventional high-temperature processes are used for stacked transistor fabrication, then device performance is achieved, but compatibility with existing CMOS process flows is reduced
Solution Approach 1:
The fabrication process is segmented into backend-of-line (BEOL) processing that is compatible with existing CMOS process flows. The stacked transistor layer is formed as a separate, additive layer using low-temperature processes that can be integrated into existing manufacturing lines without disrupting established high-temperature CMOS fabrication sequences, thereby improving adaptability while maintaining device performance.
Solution Approach 2:
The temperature parameter is changed from high-temperature (>900°C) to low-temperature (<450°C) processing. This parameter change enables compatibility with existing CMOS process flows by eliminating conflicts with previously deposited metal interconnects and dopant profiles, while device performance is maintained through optimized low-temperature processing techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for increased transistor density without degrading existing circuitry, enabling back-end processing without high-temperature-induced failures, thus enhancing the integration of transistors in semiconductor devices.
Implementation Method 1
an annealing process is performed to induce a reaction between the source/drain regions and the metal layer
Implementation Method 2
an annealing process is performed to induce a reaction between the source/drain regions and the metal layer
Data Source
AI summary
A method of forming a stacked low temperature transistor and related devices. At least some of the illustrative embodiments are methods comprising forming at least one integrated circuit device on a front surface of a bulk semiconductor substrate, and depositing an inter-layer dielectric on the at least one integrated circuit device. A semiconductor layer may then be deposited on the inter-layer dielectric. In some embodiments, a transistor is formed within the semiconductor layer. In some examples, the transistor includes a gate structure formed over the semiconductor layer as well as source/drain regions formed within the semiconductor layer disposed adjacent to and on either side of the gate structure. A metal layer may then be deposited over the transistor, after which an annealing process is performed to induce a reaction between the source/drain regions and the metal layer.