Low-Temperature TSV Sensor Packaging via Bidirectional Etching
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Solution Overview
Problem
Existing TSV technologies face challenges in integrating semiconductor sensor chips due to process limitations, such as stress caused by heat and parasitic resistance, which hinder the miniaturization and performance of sensor systems.
Innovation Solution
A bidirectional etching process using Deep Reactive Ion Etching (DRIE) and a low-temperature insulator process with parylene for forming via holes and insulating layers, along with a handle wafer process for seed layer deposition and separation, to create a specialized TSV technology for sensor chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional TSV technology is used for sensor chip integration, then vertical integration is achieved, but thermal stress and parasitic resistance increase due to high-temperature processes and thin/long TSV structures
Solution Approach 1:
The patent changes the temperature parameter from conventional high-temperature processes to low-temperature processes (below 200°C), which reduces thermal stress in the sensor chip while maintaining TSV functionality. This parameter change directly addresses the harmful thermal stress effect without sacrificing vertical integration benefits
Solution Approach 2:
The patent modifies the TSV geometry by creating shorter and wider via holes instead of thin and long structures. This dimensional change reduces the parasitic resistance of the TSV while maintaining electrical connectivity, directly solving the parasitic resistance problem in sensor integration
2Manufacturing precision
If general TSV technology is applied to thick sensor chips (5-10 times thicker than system semiconductors), then through-holes can be formed, but the DRIE process becomes complex and requires specialized scalloping reduction techniques
Solution Approach 1:
The patent applies a preliminary etching process before the main DRIE process to create a modified via hole shape that reduces scalloping. This preliminary action simplifies the subsequent DRIE process by pre-conditioning the via hole geometry, making the overall process less complex while maintaining manufacturing precision for thick sensor chips
3Ease of manufacture
If horizontal integration method is used with wirebond connection, then sensor chip and ASIC chip can be connected, but the system size increases and parasitic resistance/impedance increases due to thin and long wirebond
Solution Approach 1:
The patent transitions from horizontal integration to vertical integration by forming TSVs that penetrate through the sensor chip in the vertical direction. This dimensional change enables 3D stacking of chips, significantly reducing the system footprint and volume while maintaining ease of manufacture through standardized vertical connection processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the DRIE process, reduces thermal stress, and achieves good step coverage, enabling efficient integration of sensor chips with reduced parasitic resistance and cost, while maintaining room temperature processing.
Implementation Method 1
forming a via hole penetrating a main substrate by etching each of both surfaces of the main substrate
Implementation Method 2
forming an insulating layer on a wall surface of the via hole and the both surfaces of the main substrate
Implementation Method 3
forming a filling layer configured to cover an upper surface of the main substrate by filling metal in the via hole
Data Source
AI summary
A method for manufacturing a sensor packaging according to an exemplary embodiment of the present disclosure includes: forming a via hole penetrating a main substrate by etching each of both surfaces of the main substrate; forming an insulating layer on a wall surface of the via hole and the both surfaces of the main substrate; combining a sub-substrate on which a metallic seed layer and a bonding layer having a pattern for exposing a part of the seed layer are laminated with the main substrate; forming a filling layer configured to cover an upper surface of the main substrate by filling metal in the via hole; and removing the sub-substrate from the main substrate.