Low-Temperature Wafer Bonding for Monolithic CMUT Integration
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Solution Overview
Problem
Monolithic integration of capacitive micromachined ultrasonic transducers (CMUTs) with integrated circuits is hindered by the high temperatures required in traditional wafer bonding processes, which damage conventional electronics, limiting design flexibility and performance.
Innovation Solution
Low-temperature wafer bonding (≤450 °C) is employed to fabricate CMUTs on wafers with active electrical devices, allowing for integration of CMUT arrays with active electronics without compromising design or performance, and enabling per-cell electrode connections to substrate circuitry for enhanced flexibility and signal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional high-temperature wafer bonding (1100 °C) is used to fabricate CMUTs, then strong bonding and reliable device performance are achieved, but conventional integrated circuits are destroyed
Solution Approach 1:
The patent changes the bonding temperature parameter from traditional high temperature (1100 °C) to low temperature (≤450 °C), enabling wafer bonding to proceed without destroying the integrated circuits while still achieving sufficient bonding strength for CMUT operation
Solution Approach 2:
The patent introduces an intermediate bonding layer comprising silicon oxide and silicon nitride between the CMUT membrane wafer and the electronics wafer. This intermediate layer enables bonding at lower temperatures and protects the electronics from thermal damage while maintaining reliable mechanical and electrical connections
2Ease of manufacture
If sacrificial release fabrication is used to integrate CMUTs with electronics, then monolithic integration is achieved, but design flexibility is reduced and transduction area must be reduced to accommodate electronics
Solution Approach 1:
The patent segments the fabrication process into two separate wafers: one dedicated to CMUT membrane fabrication and another to integrated circuit fabrication. These wafers are processed independently and then bonded together, allowing each to be optimized for its specific function without compromising the other's performance or design flexibility
Solution Approach 2:
The patent transitions from planar integration (side-by-side arrangement) to three-dimensional integration (stacked arrangement with electronics beneath CMUT elements). This vertical stacking enables the electronics to occupy the space underneath the CMUT array rather than competing for lateral space, maximizing the transduction area while maintaining monolithic integration
3Strength
If high-temperature wafer bonding is used, then complete bonding strength is achieved, but process control is difficult and reproducibility is reduced
Solution Approach 1:
The patent changes the bonding temperature to a lower range (≤450 °C) where the bonding process is more controllable and less sensitive to variations in processing conditions. This lower temperature regime allows for better process control and higher reproducibility while still achieving sufficient bonding strength through the intermediate bonding layer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance, increases signal-to-noise ratio, expands bandwidth, and minimizes off-chip wiring needs, providing flexible electronic reconfiguration and improved performance by integrating CMUTs directly with electronics beneath the transducer elements.
Implementation Method 1
low temperature wafer bonding (temperature of 450 °C or less) is employed to fabricate CMUTs on a wafer that already includes active electrical devices
Implementation Method 2
Acoustic deformation of the membrane alters the electrical capacitance, thereby providing an acoustic sensing capability
Implementation Method 3
an applied electric voltage on the capacitor can alter the position of the membrane, thereby providing an acoustic generation capability
Data Source
Figure 1a~1c
Figure 2
Figure 3a~3b
AI summary
Low temperature wafer bonding (temperature of 450 °C or less) is employed to fabricate CMUTs on a wafer that already includes active electrical devices. The resulting structures are CMUT arrays integrated with active electronics by a low-temperature wafer bonding process. The use of a low-temperature process preserves the electronics during CMUT fabrication. With this approach, it is not necessary to make compromises in the CMUT or electronics designs, as is typical of the sacrificial release fabrication approach. Various disadvantages of sacrificial release, such as low process control, poor design flexibility, low reproducibility, and reduced performance are avoided with the present approach. With this approach, a CMUT array can be provided with per-cell electrodes connected to the substrate integrated circuitry. This enables complete flexibility in electronically assigning the CMUT cells to CMUT array elements.