Low-Toggling Pseudo-Random Test Pattern Generation Circuitry
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Solution Overview
Problem
Logic built-in self-test (LBIST) techniques face challenges in achieving high test coverage while minimizing scan-shift-induced switching activity, which can lead to excessive power dissipation and potential circuit damage, and existing methods often require on-chip ROM for weight assignment.
Innovation Solution
The integration of low-toggling pseudo-random test pattern generation circuitry, configurable scan chains, and weight insertion circuitry to modify bits in low-toggling pseudo-random test patterns based on background test patterns, forming weighted pseudo-random test patterns, which reduces switching activity and enhances test coverage without the need for on-chip ROM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional pseudo-random test patterns are used in LBIST, then test coverage is high, but switching activity during scan shift cycles is excessive
Solution Approach 1:
The patent changes the parameter of test pattern randomness by introducing low-toggling pseudo-random patterns that have reduced randomness compared to conventional patterns. This is achieved through controlled modification of pattern generation parameters to limit transitions between consecutive scan cycles, thereby reducing switching activity while maintaining adequate test coverage
Solution Approach 2:
The patent implements dynamic control of test pattern generation by using a control signal that switches between conventional pseudo-random patterns and low-toggling patterns. The system dynamically adjusts the randomness level based on operational requirements, allowing flexibility in balancing test coverage and power consumption
2Loss of energy
If low toggling pseudo-random test patterns are used to reduce switching activity, then power dissipation is reduced, but test coverage deteriorates
Solution Approach 1:
The patent merges two previously separate approaches: low-toggling pseudo-random pattern generation and weighted random pattern generation. By combining these techniques, the system achieves both reduced switching activity and improved test coverage simultaneously, as the weighted approach compensates for the reduced randomness in low-toggling patterns
Solution Approach 2:
The patent creates a composite test pattern approach that integrates characteristics of both low-toggling patterns and weighted random patterns. This composite method leverages the power-saving benefits of low-toggling patterns while incorporating the coverage-enhancing properties of weighted patterns through controlled bit modification
3Reliability
If weighted random pattern generation is used to improve test coverage, then detection probability increases, but device complexity increases due to on-chip ROM requirements
Solution Approach 1:
The patent extracts and removes the on-chip ROM component from traditional weighted random pattern generation systems. Instead of storing weight values in ROM, the system uses combinational logic circuits to generate weighted patterns on-the-fly, thereby reducing device complexity and area while maintaining the detection probability benefits of weighted patterns
Solution Approach 2:
The patent replaces the memory-based ROM system with a logic-based combinational circuit system. This substitution eliminates the need for physical memory storage of weight values, using instead logical operations to dynamically generate weighted patterns, thereby reducing area and complexity
Data Source
AI summary
The test circuitry according to various aspects of the presently disclosed techniques comprises: low-toggling pseudo-random test pattern generation circuitry, wherein the low-toggling pseudo-random test patterns generated by the low-toggling pseudo-random test pattern generation circuitry causing switching activity during scan shift cycles lower than pseudo-random test patterns generated by a pseudo-random pattern generator; scan chains configurable to shift in a low-toggling pseudo-random test pattern generated by the low-toggling pseudo-random test pattern generation circuitry; background chains configurable to shift in a background test pattern; and weight insertion circuitry configurable to modify a plurality of bits in the low-toggling pseudo-random test pattern based on bits in the background test pattern to form a weighted pseudo-random test pattern.