Low-Trigger High-Holding Voltage SCR for ESD Protection
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Solution Overview
Problem
Existing silicon controlled rectifiers (SCRs) often trigger on at voltages too high to effectively protect low voltage integrated circuits from electrostatic discharges (ESD) and may remain on after the ESD event, lacking a solution for low voltage triggering and high holding voltage without external circuitry.
Innovation Solution
A two-terminal SCR device with a low voltage trigger level of approximately 8V and a tunable holding voltage from 5V to 7.5V is designed, utilizing a structure with specific doping levels and dimensions in an N-Well and P-Well configuration, eliminating the need for external trigger signals and maintaining robust ESD protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional SCR structures are used, then the device is simple to manufacture, but the trigger voltage is too high to protect low voltage ICs effectively
Solution Approach 1:
The patent applies local quality by creating regions with different doping concentrations within the SCR structure. The N-well and P-well regions have specifically engineered doping levels that differ from traditional SCR designs, creating localized electrical characteristics that enable low trigger voltage while maintaining compatibility with standard CMOS fabrication processes
Solution Approach 2:
The patent implements parameter changes by modifying the doping concentrations and geometrical dimensions of the SCR device. The N-well depth (0.5-2.0 micrometers) and P-well depth (0.5-2.0 micrometers) are optimized to achieve the desired trigger voltage characteristics while remaining compatible with standard semiconductor manufacturing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides effective protection for low voltage ICs by ensuring the SCR turns off after an ESD event, with improved current handling and reduced leakage currents, while maintaining constant trigger voltage and adjustable holding voltage, enhancing the robustness of ESD protection.
Implementation Method 1
VA will reach a trigger (or snap-back) voltage level, VAB, that will produce the negative resistance snap-back curve shown in FIG. 2. VA falls to the holding voltage, VH. When VAB is reached, T1 or T2 may break down and turn on the other.
Implementation Method 2
If a separate signal is developed that forward biases the gate to cathode, T2 will turn on which in turn turns on T1 and the device triggers presenting a low impedance from the anode to the cathode.
Data Source
AI summary
A protective SCR integrated circuit device is disclosed built on adjacent N and P wells and defining an anode and a cathode. In addition to the anode and cathode contact structures, the device has an n-type stack (N+/ESD) structure bridging the N-Well and the P-Well, and a p-type stack (P+/PLDD) structure in the P-Well. The separation of the n-type stack structure and the p-type stack structure provides a low triggering voltage without involving any external circuitry or terminal, that together with other physical dimensions and processing parameters also provide a relatively high holding voltage without sacrificing the ESD protection robustness. In an embodiment, the triggering voltage may be about 8V while exhibiting a holding voltage, that may be controlled by the lateral dimension of the n-type stack of about 5-7 V.