Low-Utilization Execution Unit Power Management
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Solution Overview
Problem
The high power consumption of processor execution units, particularly those with low utilization, poses challenges in mobile applications where battery life is a concern, and powering down these units introduces performance overhead due to the time required to restore architecturally-visible state.
Innovation Solution
A processor design that includes a power management circuit to detect inactivity in low-utilization execution units, copy their architecturally-visible state to a retention circuit in a different power domain, and power them down, while maintaining the state for quick restoration when needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If execution units are powered down to reduce power consumption, then power requirements are reduced, but performance is worsened due to time required to restore architecturally-visible state
Solution Approach 1:
The execution unit is divided into two separate circuits: a high-utilization execution unit circuit and a low-utilization execution unit circuit. This segmentation allows the system to dynamically switch between circuits based on utilization patterns, powering down the low-utilization circuit when not needed while maintaining the high-utilization circuit ready for immediate execution, thus resolving the contradiction between power savings and performance.
Solution Approach 2:
The system performs preliminary actions by detecting inactivity patterns and proactively copying architecturally-visible state to a retention circuit before powering down the execution unit. This preliminary state preservation enables rapid power-up and resumption of execution without significant performance penalty, as the state is already prepared for quick restoration when the execution unit is needed again.
2Productivity
If execution units are kept active to maintain performance, then productivity is improved, but power requirements increase
Solution Approach 1:
The system implements dynamic power management by continuously monitoring utilization patterns of execution units and dynamically adjusting their power states. The power management circuit detects when execution units transition from high to low utilization and automatically powers them down, while maintaining the ability to quickly reactivate them when needed. This dynamic approach optimizes the balance between performance and power consumption in real-time.
Solution Approach 2:
The system changes the operational parameters of execution units by introducing a retention circuit that preserves architecturally-visible state at different power states. When execution units are powered down, their state parameters are maintained in the retention circuit, allowing the execution units to be rapidly reactivated with minimal parameter restoration time, thus enabling aggressive power savings without permanent performance degradation.
3Use of energy by moving object
If low-utilization execution units are powered down, then power requirements are reduced, but device complexity increases due to retention circuit requirements
Solution Approach 1:
The retention circuit is designed with multi-functionality to reduce overall device complexity. It serves multiple purposes: preserving architecturally-visible state during power-down, enabling rapid power-up recovery, and supporting both high-utilization and low-utilization execution unit circuits. This universal retention infrastructure reduces the need for separate complex state management mechanisms for each execution unit, thereby offsetting the added complexity with functional consolidation.
Data Source
AI summary
A processor includes an instruction issue circuit, and high-utilization and low-utilization execution unit circuits coupled to execute instructions received from the instruction issue unit. On average, utilization of the low-utilization execution unit circuit is lower than utilization of the high-utilization execution unit circuit. The processor also includes a retention circuit coupled to a different power domain than the low-utilization execution unit circuit, and a power management circuit. The power management circuit may be configured to detect that inactivity of the low-utilization execution unit circuit satisfies a threshold inactivity level; upon detecting that the threshold inactivity level is satisfied, cause architecturally-visible state of the low-utilization execution unit circuit to be copied to the retention circuit; and subsequent to copying of the architecturally-visible state to the retention circuit, cause the low-utilization execution unit circuit to enter a power-off state, where the retention circuit retains stored data during the power-off state.