Low Viscosity Planarization for Non-Volatile Memory Edge Thinning
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Solution Overview
Problem
In semiconductor device manufacturing, particularly for non-volatile memory cells, there is a challenge in achieving effective planarization while minimizing topography variations and avoiding edge thinning issues, especially in high-density devices, where high viscosity planarization materials often require multiple applications and dam structures, increasing device size and manufacturing time.
Innovation Solution
The use of a low viscosity planarization material with a viscosity of less than 1.2 centipoise, such as a carbon backbone polymer, allows for conformal edge formation without a dam structure, enabling efficient planarization and reducing device size by eliminating the need for additional space-consuming features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high viscosity planarization material is used, then planarization coverage is improved, but multiple applications and dam structures are required, increasing device size and manufacturing time
Solution Approach 1:
The patent changes the viscosity parameter of the planarization material from high viscosity to low viscosity (less than 1.2 centipoise). This parameter change enables the material to achieve adequate planarization coverage in a single application without requiring dam structures, thereby reducing both device size and manufacturing time while maintaining planarization effectiveness
2Manufacturing precision
If high viscosity planarization material is used, then planarization coverage is improved, but device size increases due to requirement of dam structures
Solution Approach 1:
By changing the viscosity parameter to low viscosity (less than 1.2 centipoise), the planarization material can be applied without dam structures. This eliminates the need for additional space-consuming features while maintaining adequate planarization coverage, resulting in a 10%-20% smaller device area
Solution Approach 2:
The patent extracts and eliminates the dam structure requirement from the planarization process. By using low viscosity material that can be effectively applied without dams, the unnecessary structural elements are removed, reducing device footprint and simplifying the overall device architecture
3Manufacturing precision
If high viscosity planarization material is used, then planarization coverage is improved, but number of applications increases, increasing manufacturing complexity
Solution Approach 1:
Changing the viscosity parameter to low viscosity (less than 1.2 centipoise) enables single-application planarization. This simplifies the manufacturing process by eliminating multiple application steps and associated processing complexity, while still achieving adequate planarization coverage for high-density devices
Data Source
AI summary
A method of manufacturing a non-volatile memory semiconductor device includes forming a plurality of memory cells on a non-volatile memory cell area of a semiconductor substrate, and forming a conductive layer over the plurality of memory cells. A first planarization layer of a planarization material having a viscosity of less than about 1.2 centipoise is formed over the plurality of memory cells. A planarization operation is performed on the first planarization layer and the conductive layer, thereby removing an upper region of the first planarization layer and an upper region of the conductive layer. Portions of a lower region of the conductive layer are completely removed between the memory cells.