Low-Voltage Cache Fault Detection Through Data Inversion
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Solution Overview
Problem
Modern computing devices face challenges in maintaining reliable cache operation at low voltage levels, as reduced supply voltage increases susceptibility to bit errors and masked faults, which can lead to incorrect assessment of cache line reliability.
Innovation Solution
The implementation of a cache system that inverts data upon first read after a fill, regenerates error correction bits, and adjusts error protection levels based on bit error changes during subsequent reads to uncover and mitigate masked faults, ensuring reliable operation at low voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the supply voltage for cache memory circuits is reduced to lower power consumption, then power consumption decreases, but the memory circuits become more susceptible to bit errors and masked faults
Solution Approach 1:
The patent applies preliminary action by inverting cache line data and regenerating error correction codes before normal reads can mask faults. This proactive transformation ensures that when data is later read, the error detection mechanisms can identify faults that would otherwise be hidden by the original data values, thereby maintaining reliability at low voltage
Solution Approach 2:
The patent changes the data state parameter by inverting bits (0 becomes 1, 1 becomes 0) and regenerating error correction codes. This parameter transformation allows the error detection system to identify masked faults that would not be detectable in the original data state, resolving the reliability issue while maintaining low voltage operation
2Measurement precision
If error correction codes are regenerated after data inversion to detect masked faults, then fault detection capability improves, but cache operation complexity increases
Solution Approach 1:
The patent implements feedback by using error correction codes to detect faults in inverted data, then using this detection information to determine whether to invert subsequent writes to the same cache line. This feedback loop enables automatic adaptation to detected faults, improving detection accuracy while managing complexity through systematic control
Solution Approach 2:
The cache system performs self-diagnosis and self-correction by automatically detecting masked faults through inverted data reads and adjusting its own error correction strategy. The system serves itself by identifying and compensating for its own defects without external intervention, thereby improving fault detection while containing complexity within the cache controller
Data Source
AI summary
Systems, apparatuses, and methods for implementing masked fault detection for reliable low voltage cache operation are disclosed. A processor includes a cache that can operate at a relatively low voltage level to conserve power. However, at low voltage levels, the cache is more likely to suffer from bit errors. To mitigate the bit errors occurring in cache lines at low voltage levels, the cache employs a strategy to uncover masked faults during runtime accesses to data by actual software applications. For example, on the first read of a given cache line, the data of the given cache line is inverted and written back to the same data array entry. Also, the error correction bits are regenerated for the inverted data. On a second read of the given cache line, if the fault population of the given cache line changes, then the given cache line's error protection level is updated.