Low-Voltage Column Select Driver for Far-Edge Memory Access

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Solution Overview

Problem

As DRAM density increases, column select drivers face challenges in driving column select signals from one rail potential to another rail potential at the far edge of the memory bank, leading to insufficient signal levels and delayed charging/discharging times, which affect data writing and reading from memory cells at the far edge.

Innovation Solution

Implementing a column decoder with a low-voltage architecture that uses multiple-step voltage levels and boost signals to enhance rise and fall times, along with a latch style CS driver architecture that does not require level shifters, and a single-sided CS driver to ensure uniform pulse width and reduced area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory device density is increased, then storage capacity is improved, but signal level and charging/discharging speed at far edge deteriorate

Engineering Contradiction:

Improvememory densityVSAvoidsignal level at far edge

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The column select driver is divided into multiple segments along the column select line, with each segment having its own driver circuit. This segmentation allows each driver to control a localized portion of the memory bank, ensuring sufficient signal strength is maintained throughout the entire bank even as density increases.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Column select repeaters are introduced as intermediary elements along the column select line. These repeaters receive weakened signals from distant drivers and regenerate them to full strength, acting as mediators that maintain signal integrity across the expanded memory bank distance.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Quantity of substance

If memory device density is increased, then storage capacity is improved, but charging/discharging time at far edge increases

Engineering Contradiction:

Improvememory densityVSAvoidcharging/discharging time

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The column select driver pre-charges the column select line to a predetermined voltage level before actual column selection occurs. This preliminary action reduces the time required for rapid voltage transitions during normal operation, compensating for increased distances in high-density configurations.

Inventive Principle:

Principle #10Preliminary action

3Device complexity

If traditional column select driver architecture is used, then design simplicity is maintained, but signal drive capability at far edge is insufficient

Engineering Contradiction:

Improvedriver architecture complexityVSAvoidsignal drive capability

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention changes key parameters of the driver architecture including voltage levels (using elevated voltages for far-edge drivers), current capabilities (providing higher drive current), and timing characteristics (adjusting rise/fall times). These parameter changes enable reliable signal driving across high-density memory banks.

Inventive Principle:

Principle #35Parameter changes

4Reliability

If level shifters are added to drive far edge signals, then signal level is improved, but device area and manufacturing cost increase

Engineering Contradiction:

Improvesignal levelVSAvoidchip area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The column select driver circuits are designed to perform multiple functions: they provide signal amplification, voltage level adjustment, and timing control all within a single integrated circuit block. This multi-functionality eliminates the need for separate level shifter components, reducing overall chip area.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The invention merges the column select driver functionality with the column decoder logic into an integrated architecture. By combining these functions and eliminating discrete level shifter components, the design achieves high signal drive capability while minimizing chip area and manufacturing complexity.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20250299724A1Low-voltage column select driver for high-density memory device

Publication Date: 2025.09.25 MICRON TECHNOLOGY INC

AI summary

A memory device includes a column decoder configured to decode a column address. The column decoder includes a column select driver configured to modulate a column select signal based on the column address in order to activate or deactivate a plurality of column selection circuits coupled to a column select line. The column select signal includes an activation pulse for activating the plurality of column selection circuits during an activation interval. The activation pulse includes a first portion having a positive boost signal level and a second portion having an activation signal level that is less than the positive boost signal level. The column select driver is configured to generate the first portion of the activation pulse for a first duration of the activation interval, and, following the first duration, generate the second portion of the activation pulse for a second duration of the activation interval.