Low-Voltage Dynamic Comparator With Resistor-Coupled CMOS Feedback

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Solution Overview

Problem

Conventional dynamic comparators fail to operate effectively at low power supply voltages below the threshold voltages of PMOS and NMOS transistors, leading to insufficient current passage and unstable output voltages, which hinders the determination of input voltage magnitudes.

Innovation Solution

Incorporating a first resistor between a PMOS and an NMOS transistor and a second resistor between another PMOS and NMOS transistor, with specific gate connections to ensure sufficient voltage application to the transistors, allowing the comparator to function correctly even at low power supply voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional dynamic comparator is used with CMOS inverters, then the comparator can operate at high power supply voltages, but it fails to pass sufficient current and stabilize outputs at low power supply voltages below transistor threshold voltages

Engineering Contradiction:
Improvecomparator operation reliabilityVSAvoidpower supply voltage
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

Resistors are introduced as intermediary elements between the differential pair transistors and the CMOS inverter loads. These resistors act as mediators that regulate current flow and voltage distribution, enabling the comparator to function reliably at low supply voltages by preventing direct voltage drops that would otherwise prevent transistor activation

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention changes the electrical parameters of the circuit by adding resistive elements that modify the voltage-current characteristics. This allows the circuit to operate in a low-voltage regime where the original CMOS inverter configuration would fail, effectively changing the operating point parameters to match low-voltage conditions

Inventive Principle:
Principle #35Parameter changes

2Productivity

If positive feedback is applied to CMOS inverters at low voltage, then output switching should occur, but outputs remain unstable and determination time is prolonged

Engineering Contradiction:
Improvedetermination speedVSAvoidoutput voltage stability
Core Design Contradiction:
ProductivityVSStability of the object's composition

Solution Approach 1:

The resistors serve as intermediary elements that stabilize the interaction between the differential pair and the CMOS inverters. They provide controlled current paths that prevent oscillation and ensure stable voltage levels at the inverter inputs, enabling reliable positive feedback operation at low voltages

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The resistors provide beforehand cushioning by limiting current surges and preventing excessive voltage drops before they can occur. This protective effect ensures that the CMOS inverters receive stable voltage inputs even under low-voltage conditions, preventing output instability before it manifests

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS8884653B2Comparator and ad converter provided therewith
Publication Date: 2014.11.11 MITSUMI ELECTRIC CO LTD
  • US8884653B2 patent drawing
  • US8884653B2 patent drawing
  • US8884653B2 patent drawing

AI summary

Disclosed is a comparator including a switching element, a differential pair, and a positive feedback part, the positive feedback part including a first CMOS inverter and a second CMOS inverter, the first CMOS inverter including a first element for providing a potential difference between a first PMOS transistor and a first NMOS transistor, the second CMOS inverter including a second element for providing a potential difference between a second PMOS transistor and a second NMOS transistor, a higher potential side of the first element being connected to a gate of the second NMOS transistor, a lower potential side of the first element being connected to a gate of the second PMOS transistor, a higher potential side of the second element being connected to a gate of the first NMOS transistor, and a lower potential side of the second element being connected to a gate of the first PMOS transistor.