Low-Voltage EEPROM Array With Integrated Transistors
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Solution Overview
Problem
Conventional EEPROM arrays have a larger area and higher cost due to the need for separate transistors during bit-erase activities and lack a low-voltage byte-write and byte-erase functionality.
Innovation Solution
A low-voltage EEPROM array design featuring parallel bit lines, word lines, and common source lines with symmetrical sub-memory arrays, utilizing n-type or p-type FETs and specific voltage conditions for write and erase operations without isolation transistors, allowing for byte-write and byte-erase functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional EEPROM structure with separate transistors is used for bit-erase activity, then byte-write and byte-erase functions are achieved, but area increases and cost increases
Solution Approach 1:
The patent merges the selection transistor and memory transistor into a single integrated structure. The control gate serves dual functions as both the selection gate and memory storage element, eliminating the need for separate transistors. This consolidation maintains byte-write and byte-erase capabilities while significantly reducing the area occupied by each memory cell.
Solution Approach 2:
The control gate is designed to perform multiple functions: it acts as the selection transistor gate for addressing specific memory cells, and simultaneously serves as the memory transistor gate for data storage. This multi-functional design eliminates redundant components and reduces overall array area while preserving full EEPROM functionality.
2Ease of operation
If conventional EEPROM structure with separate transistors is used, then byte-write and byte-erase functions are achieved, but manufacturing cost increases
Solution Approach 1:
By combining the selection transistor and memory transistor into a single integrated structure, the patent reduces the total number of transistor components that need to be fabricated. This consolidation simplifies the manufacturing process, reduces material usage, and lowers production costs while maintaining full EEPROM operational capabilities.
Solution Approach 2:
The patent extracts and eliminates the redundant selection transistor component from the conventional EEPROM structure. By removing this unnecessary separate component and integrating its function into the control gate, the design simplifies manufacturing and reduces costs associated with fabricating and assembling multiple discrete transistors.
3Area of stationary object
If flash memory structure is used, then area is reduced and cost is reduced, but only large-area erasion is supported
Solution Approach 1:
The patent segments the erasure capability into two levels: individual byte erasure for specific memory cells and large-area erasure for multiple cells. The integrated transistor structure enables precise control at the byte level while maintaining the capability for broader erasure operations, thus providing both the area efficiency of flash memory and the operational versatility of EEPROM.
Solution Approach 2:
The memory structure is designed to support multiple erasure modes: it can perform byte-level erasure of specified memory cells and also support large-area erasure of multiple cells simultaneously. This multi-functional design provides the adaptability of EEPROM while maintaining the compact area of flash memory architecture.
Data Source
AI summary
A low-voltage EEPROM array, which has a plurality of parallel bit lines, parallel word lines and parallel common source lines is disclosed. The bit lines include a first bit line. The word lines include a first word line and a second word line. The common source lines include a first common source line and a second common source line. The low-voltage EEPROM array also has a plurality of sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell connects with the first bit line, the first common source line and the first word line. The second memory cell connects with the first bit line, the second common source line and the second word line. The first and second memory cells are symmetrical and arranged between the first and second common source lines.