Low-Voltage LDO Regulator With Coarse-Fine Gate Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional voltage regulators face challenges in operating efficiently at low voltages, particularly in highly integrated and portable semiconductor devices, where power consumption needs to be minimized, and they often suffer from high transient response, ripple, and power supply rejection ratio (PSRR) issues.
Innovation Solution
A low dropout (LDO) regulator is designed with power transistors, a voltage comparing unit, a digital control unit, and a gate driving unit that generates a gating signal based on the difference between the output voltage and a reference voltage, using either the input voltage or its negative for effective control, enabling a coarse and fine loop control mechanism to stabilize output voltage across varying ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional voltage regulators are used to operate at low voltage, then power consumption is reduced, but transient response becomes slower and ripple increases
Solution Approach 1:
The patent divides the power transistor gate control into multiple segments: a first gate electrode receives a first control signal for coarse voltage regulation, while a second gate electrode receives a second control signal for fine voltage regulation. This segmentation allows the regulator to achieve fast transient response through coordinated control of multiple gate segments, while maintaining low power consumption through efficient voltage management.
2Use of energy by moving object
If conventional voltage regulators are used to operate at low voltage, then power consumption is reduced, but device size becomes larger
Solution Approach 1:
The patent implements a dual-gate transistor structure where the same power transistor serves multiple functions: the first gate electrode handles coarse voltage regulation while the second gate electrode handles fine regulation. This multi-functionality eliminates the need for separate regulation circuits, thereby reducing overall device area while maintaining low power consumption capabilities.
3Use of energy by moving object
If conventional voltage regulators are used to operate at low voltage, then power consumption is reduced, but stability deteriorates
Solution Approach 1:
The patent employs feedback mechanisms where control signals are generated based on the output voltage to maintain stability. The first and second control signals are adjusted according to the output voltage conditions, ensuring stable regulation even at low input voltages while keeping power consumption low.
4Device complexity
If conventional voltage regulators are used, then circuit structure is simpler, but switching noise increases
Solution Approach 1:
The patent dynamically controls the gate voltages of the power transistor through two independent control signals that can be adjusted in real-time based on operating conditions. This dynamic control allows the regulator to minimize switching noise by optimizing the switching behavior of the power transistor, while maintaining a relatively simple overall circuit structure.
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
A low dropout (LDO) regulator includes: one or more power transistors configured to dispose between an input node and an output node, wherein the input node is a node to which an input voltage is applied and the output node is a node from which an output voltage is output; a voltage comparing unit configured to generate a comparative signal based on a difference between the output voltage and a first reference voltage; a digital control unit configured to generate a control signal for gating of the one or more power transistors in response to the comparative signal; and a gate driving unit configured to output a gating signal for the one or more power transistors in response to the control signal, wherein the gating signal is corresponding to one of the input voltage and a negative of the input voltage.