Low-Voltage Level Shifter With Strong Edge Transitions
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Solution Overview
Problem
Designing a level-shifter for low-voltage signals is challenging due to high power consumption and stringent device matching requirements in existing amplifier-based and cross-coupled latch-based solutions, especially when the binary-high state is near or below the transistor threshold voltage.
Innovation Solution
A level-shifter design that includes a first inverter, NMOS transistors to discharge internal and inverted level-shifter nodes, and a second inverter powered by a higher voltage to produce a strong rising and falling edge, with a buffer to create a feedback signal, allowing for efficient level shifting with relaxed transistor matching requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If amplifier-based or cross-coupled latch-based level-shifters are used to level shift low-voltage signals, then the level shifting function is achieved, but power consumption increases excessively
Solution Approach 1:
The patent changes the operating parameters by using a latch-based design with specific transistor sizing ratios (e.g., input transistor width-to-length ratio between 50:1 to 200:1) and voltage threshold selection to achieve low-voltage operation while maintaining reliability. The design operates at voltages barely satisfying or slightly less than transistor threshold voltage by optimizing device parameters.
Solution Approach 2:
The level-shifter is segmented into distinct functional blocks: an input stage with first and second transistors, a latch stage with third and fourth transistors, and an output stage with fifth and sixth transistors. This segmentation allows each stage to be optimized independently for low power consumption while maintaining overall reliability.
2Device complexity
If amplifier-based or cross-coupled latch-based level-shifters are used, then level shifting is achieved, but the number of devices required increases
Solution Approach 1:
The patent merges the input buffering function and level shifting function into a single integrated latch-based circuit. The first and second transistors serve both as input devices and as part of the latch structure, eliminating the need for separate buffering stages and reducing total device count while maintaining reliability.
Solution Approach 2:
The third and fourth transistors in the latch stage serve multiple functions: they provide regenerative feedback for signal restoration, act as switching elements for level translation, and provide input impedance control. This multi-functionality reduces the need for additional dedicated components.
3Reliability
If amplifier-based or cross-coupled latch-based level-shifters are used for low-voltage signals, then level shifting occurs, but duty-cycle distortion increases
Solution Approach 1:
The latch-based design uses periodic switching action where the third and fourth transistors are alternately activated based on the input signal transitions. This periodic operation restores the duty cycle at each transition while consuming power only during switching events, not during steady-state operation.
Solution Approach 2:
The patent implements regenerative feedback through the cross-coupled latch structure where the output of the fifth transistor feeds back to control the third transistor, and the output of the sixth transistor feeds back to control the fourth transistor. This feedback mechanism actively corrects duty-cycle distortion by reinforcing the intended signal transitions.
Data Source
AI summary
A level-shifter is provided with a first transistor and a second transistor. The first transistor functions to discharge an internal node responsive to an assertion of an inverted input signal to a first power supply voltage. A second transistor functions to discharge an inverted level-shifter output signal responsive to an assertion of an input signal to the first power supply voltage. An inverter inverts the inverted level-shifter output signal to form a level-shifter output signal that is asserted to a second power supply voltage responsive to the assertion of the input signal.