Low-Voltage Level Shifter With Overvoltage Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional level shifter designs face electrical overstress issues due to the lack of support for high voltage transistors in newer technology nodes, particularly when transitioning between 1.8V I/O voltage domains and 0.75V core voltage domains, as seen in FinFET technology nodes, leading to device overstress problems.
Innovation Solution
A voltage level-shifting circuit incorporating a transistor overvoltage protection circuit with 1.5V rated PMOS and NMOS transistors, along with a supply loss protection circuit, is employed to safely transition signals between the I/O and core voltage domains, using a second voltage supply lower than the I/O voltage level and enabling signals to manage transistor operation within safe voltage ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If higher voltage devices are used to support 1.8V I/O voltage domain, then voltage level shifting capability is improved, but device availability deteriorates due to lack of support in newer FinFET technology nodes
Solution Approach 1:
The patent changes the voltage parameter of the transistors from high voltage (1.8V) to low voltage (1.5V rated) devices. By modifying the voltage rating parameter and implementing protection circuits, the design adapts to newer FinFET technology nodes that no longer support high voltage transistors, while still achieving the required voltage level shifting functionality between I/O and core domains.
2Ease of manufacture
If 1.5V rated transistors are used instead of higher voltage devices, then device compatibility with newer technology nodes is improved, but electrical overstress risk increases when operating in 1.8V I/O voltage domain
Solution Approach 1:
The patent applies preliminary protective actions by implementing overvoltage protection circuits and supply loss protection circuits before the electrical overstress can occur. These protection mechanisms are designed in advance to prevent voltage exceeding the 1.5V rating of the transistors, thereby eliminating the harmful effect of electrical overstress while maintaining compatibility with newer technology nodes.
Solution Approach 2:
The patent introduces intermediary protection circuits that mediate between the 1.8V I/O voltage domain and the 1.5V rated transistors. These intermediary circuits ensure that the transistors never experience voltage beyond their rated tolerance, effectively isolating them from harmful overvoltage conditions while still enabling voltage level shifting functionality.
3Device complexity
If conventional level shifter designs are implemented without protection circuits, then circuit simplicity is improved, but reliability deteriorates due to transistor overstress in cross-domain operations
Solution Approach 1:
The patent implements beforehand cushioning by adding protection circuits that cushion the transistors against overvoltage stress before it can cause damage. The overvoltage protection circuit and supply loss protection circuit are designed to activate preemptively, protecting the transistors during cross-domain voltage transitions and supply voltage fluctuations, thereby significantly improving reliability.
Data Source
AI summary
A voltage level-shifting circuit for an integrated circuit includes an input terminal receiving a voltage signal referenced to an input/output (I/O) voltage level. A transistor overvoltage protection circuit includes a first p-type metal oxide semiconductor (PMOS) transistor includes a source coupled to the second voltage supply, a gate receiving an enable signal, and a drain connected to a central node. A first n-type metal oxide semiconductor (NMOS) transistor includes a drain connected to the central node, a gate connected to the input terminal, and a source connected to an output terminal. A second NMOS transistor includes a drain connected to the input terminal, a gate connected to the central node, and a source connected to the output terminal.