Low Voltage Programming of Non-Volatile Memory Cells

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Solution Overview

Problem

Current non-volatile memory programming techniques face challenges in preventing unintentional programming or erasure of unselected cells due to high electric fields and scaling issues in NAND memory devices, leading to disturbances like Gate Induced Drain Leakage (GIDL) and unintended programming through Fowler-Nordheim tunneling, source side injection, and channel hot-electron injection.

Innovation Solution

A low voltage programming method that injects hot carriers from a drain region of a neighboring memory cell into the floating gate of a selected memory cell by applying specific voltage biases to wordlines and bitlines, including a high passing voltage to unselected wordlines and a program voltage to the selected wordline, while ramping the gate node voltage of the neighboring wordline from 0V to a read voltage, thereby reducing the risk of programming disturbs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If high voltage programming is used to program selected memory cells, then programming speed and efficiency are improved, but programming disturbs such as GIDL and unintended programming of unselected cells increase

Engineering Contradiction:
Improveprogramming speedVSAvoidprogramming disturb
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent applies different voltage levels to different wordlines: high voltage (Vpgm) to the selected wordline for efficient programming, and low voltage (Vread or 0V) to unselected wordlines to prevent disturbs. This localized voltage differentiation allows fast programming of selected cells while protecting unselected cells from GIDL and unintended programming

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the wordline voltage distribution into distinct levels based on selection status. By dividing wordlines into selected (high voltage) and unselected (low voltage) groups, the system achieves both high programming efficiency for selected cells and low disturb for unselected cells, resolving the contradiction between speed and reliability

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If device geometries are scaled down to increase storage capacity, then memory density is improved, but electric fields become more concentrated leading to increased programming disturbs

Engineering Contradiction:
Improvememory densityVSAvoidprogramming disturb
Core Design Contradiction:
Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The patent changes the voltage parameter distribution across the memory array to compensate for scaling effects. By maintaining low voltage on unselected wordlines even as devices scale down, the patent prevents the concentration of electric fields from causing GIDL and other disturbs, while still enabling high-density storage through continued scaling of selected cells

Inventive Principle:
Principle #35Parameter changes

3Reliability

If voltage to unselected wordlines is increased to prevent channel boosting insufficiency, then program disturb inhibition is improved, but unintentional programming of unselected cells occurs due to tunneling

Engineering Contradiction:
Improveprogram disturb inhibitionVSAvoidunintentional programming
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent dynamically adjusts unselected wordline voltage based on the specific programming operation being performed. During programming, unselected wordlines are held at Vread or 0V to prevent both insufficient boosting and unintended programming. The voltage is changed in response to the operation type, allowing the system to adapt to different conditions and avoid both extremes

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively prevents programming disturbs and ensures reliable programming of selected memory cells at low voltages, maintaining the integrity of unselected cells and reducing the impact of high electric fields, even as device geometries scale down.

Implementation Method 1

Programming is generally accomplished by using one of three major mechanisms: Fowler-Nordheim (FN) tunneling, source side [hot-electron] injection (SSI) and channel, or substrate, hot-electron injection (CHEI or SHEI).

Methodology Applied
Scientific EffectSource side injection:

Implementation Method 2

Programming is generally accomplished by using one of three major mechanisms: Fowler-Nordheim (FN) tunneling, source side [hot-electron] injection (SSI) and channel, or substrate, hot-electron injection (CHEI or SHEI).

Methodology Applied
Scientific EffectHot-electron injection:

Implementation Method 3

Programming is generally accomplished by using one of three major mechanisms: Fowler-Nordheim (FN) tunneling, source side [hot-electron] injection (SSI) and channel, or substrate, hot-electron injection (CHEI or SHEI).

Methodology Applied
Scientific EffectFowler-Nordheim tunneling:

Implementation Method 4

Programming is generally accomplished by using one of three major mechanisms: Fowler-Nordheim (FN) tunneling, source side [hot-electron] injection (SSI) and channel, or substrate, hot-electron injection (CHEI or SHEI).

Methodology Applied
Scientific EffectChannel hot-electron injection:

Implementation Method 5

Programming is generally accomplished by using one of three major mechanisms: Fowler-Nordheim (FN) tunneling, source side [hot-electron] injection (SSI) and channel, or substrate, hot-electron injection (CHEI or SHEI).

Methodology Applied
Scientific EffectSubstrate hot-electron injection:

Data Source

PatentEP2102868B1Method and system of low voltage programming of non-volatile memory cells
Publication Date: 2016.02.24 SANDISK TECHNOLOGIES LLC
  • EP2102868B1 patent drawingFigure 1
  • EP2102868B1 patent drawingFigure 2
  • EP2102868B1 patent drawingFigure 3

AI summary

A low voltage method and system of programming a selected non-volatile memory cell in a memory array having a gate node coupled to a wordline WL(n) and a drain node connected to a selected bitline by injecting hot carriers from a drain region of an injecting memory cell having a gate node coupled to a next neighbor wordline WL(n-1) into a floating gate of the selected non-volatile memory cell on the wordline WL(n).