Low-Voltage Signal Sampling Circuit With Two-Stage Latch Gain
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Solution Overview
Problem
Existing signal sampling devices struggle to adequately amplify sampled data signals in low-voltage environments, leading to insufficient amplitude differences within the original operating period.
Innovation Solution
A signal sampling device is designed with an input circuit activated in a first period to generate output signals, and a latch circuit activated in a later second period to further process these signals, effectively increasing the gain of the latch circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a two-tail current source sampling amplifier is used in low-voltage environments, then the circuit can operate in low-voltage conditions, but the data sampling requires greater time and the latch cannot adequately amplify sampled data signals to sufficient amplitude difference within the original operating period
Solution Approach 1:
The patent divides the amplification process into two distinct stages: a first amplification stage that operates during the first clock period to perform initial signal conditioning, and a second amplification stage that operates during the second clock period to provide additional gain. This segmentation allows each stage to be optimized for its specific function and timing, resolving the contradiction by achieving sufficient total amplification gain through sequential operation rather than requiring excessive time in a single stage.
Solution Approach 2:
The patent employs periodic clock signals to control the operation of the sampling amplifier and latch circuit. The first clock period triggers the initial sampling and first-stage amplification, while the second clock period triggers the second-stage amplification. This periodic action enables the circuit to achieve adequate amplitude difference through multiple sequential amplification cycles, maintaining low-voltage operation while improving overall amplification gain within the extended operating period.
2Productivity
If multiple cascaded transistors are used to increase amplification gain, then the gain is improved, but the circuit structure becomes unsuitable for low-voltage application environments
Solution Approach 1:
The patent employs dynamic clocking schemes where the sampling amplifier and latch circuit are activated at different times through separate clock periods. The first clock period enables the sampling phase and initial amplification, while the second clock period enables the second-stage amplification. This dynamic time-division approach allows the circuit to achieve high amplification gain through sequential operation rather than requiring excessive static transistor cascading, thereby maintaining compatibility with low-voltage environments.
Solution Approach 2:
The patent changes the operational parameters of the amplification circuit by introducing a two-period clocking scheme. During the first period, the circuit operates in sampling mode with specific voltage levels and transistor states. During the second period, the circuit transitions to a second-stage amplification mode with different voltage levels and transistor states. This parameter change approach enables sufficient amplification gain to be achieved through temporal separation of operations rather than through excessive transistor cascading that would compromise low-voltage adaptability.
Data Source
AI summary
A signal sampling device includes an input circuit and a latch circuit. The input circuit is activated in a first period according to a first clock signal to generate a plurality of first output signals according to a plurality of input signals. The latch circuit is activated in a second period according to a second clock signal to generate a plurality of second output signals according to the plurality of first output signals,