Low-Voltage Shared Counter Circuit for Fast Column-Parallel ADCs
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Solution Overview
Problem
Column-parallel single-slope analog-to-digital converters (ADCs) face challenges in achieving high resolution and fast conversion rates due to high power dissipation and substrate noise, particularly when using a shared counter, which limits the speed and capacitive load on counter output bits.
Innovation Solution
A shared counter circuit that outputs low-voltage signals to multiple ADC columns, utilizing regenerative latches and low-voltage driver circuits to reduce power dissipation and substrate noise, allowing for fast counting while maintaining high resolution and conversion speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a shared counter is used to reduce power dissipation and substrate noise, then power consumption decreases, but the capacitive load on counter output bits increases and counting speed is limited
Solution Approach 1:
The patent segments the counter output signal path into two distinct parts: a low-voltage shared counter that generates the count signal, and separate regenerative latches in each ADC column that restore the signal to full voltage swing. This segmentation allows the shared counter to operate at low voltage for reduced power consumption while the regenerative latches provide the necessary signal restoration for high-speed operation, effectively resolving the contradiction between power dissipation and counting speed.
2Device complexity
If a shared counter is used to serve multiple ADC columns, then device complexity is reduced, but the capacitive load on counter output bits increases
Solution Approach 1:
The patent introduces regenerative latches as intermediary elements between the shared low-voltage counter and the ADC columns. These latches act as mediators that receive the low-voltage counter signal, regenerate it to full voltage swing, and drive the ADC column inputs. This intermediary approach allows the shared counter to serve multiple columns without directly driving their full capacitive loads, thereby reducing the harmful capacitive load effect on the counter while maintaining device complexity benefits.
3Speed
If high-speed counter operation is achieved by placing one counter per column, then counting speed increases, but power dissipation and substrate noise become significant
Solution Approach 1:
The patent merges the counting function into a single shared low-voltage counter that serves all ADC columns, eliminating the need for separate counters in each column. By combining the counting function and using low-voltage operation, the patent achieves high counting speed through the shared counter while significantly reducing power dissipation compared to having multiple high-speed counters, one per column.
Data Source
AI summary
A shared counter circuit for a column-parallel single-slope ADC includes an n-bit counter; n low-voltage (LV) drivers connected to receive respective counter output bits and to provide a logic high or logic low output signal which tracks the received bit, the voltage difference between the logic high and logic low output signals being less than Vdd; and a plurality of sets of regenerative latches powered by a supply voltage Vdd, each of which receives an output from a respective LV driver and latches and regenerates the received output as a rail-to-rail CMOS signal upon the occurrence of a trigger event. One typical trigger event occurs when a periodic ramp voltage exceeds an input voltage provided to the ADC which may originate, for example, from the columns of a photodetector array.