Low-Voltage VGA Circuit With Low Phase Sensitivity
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Solution Overview
Problem
Variable gain amplifiers (VGAs) in phased array antennas suffer from increased parasitic capacitance, poor linearity performance, and significant phase variations relative to gain settings, leading to phase incoherence and the need for continual recalibrations, which degrade the performance and increase the complexity and cost of the antenna's circuitry.
Innovation Solution
The development of digitally controlled VGAs with low voltage capabilities and constant current consumption, featuring a consistent number of 'on' transistors across all gain settings, reduced parasitic capacitance, and constant impedance, which provide accurate gain steps and minimize phase sensitivity to gain changes, thereby maintaining low distortion levels even at maximum gain without requiring power back-off for linear performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If variable gain amplifiers are used in phased array antennas, then gain control and dynamic performance are improved, but parasitic capacitance increases and phase variations occur
Solution Approach 1:
The patent implements a dynamically adjustable resistor ladder network where resistors can be switched in and out based on desired gain settings. This dynamic configuration allows the VGA to adjust gain while maintaining consistent impedance and minimizing parasitic capacitance effects across different gain states, resolving the contradiction between adaptability and harmful factors
Solution Approach 2:
The patent changes the resistance values in the ladder network to control gain while maintaining constant impedance at critical nodes. By carefully selecting resistor values and using switching mechanisms that maintain impedance continuity, the design achieves variable gain without significant phase variations or increased parasitic capacitance
2Productivity
If variable gain amplifiers are used to enhance dynamic performance, then signal strength adaptation is improved, but phase incoherence and linearity performance deteriorate
Solution Approach 1:
The patent maintains equipotential conditions at critical nodes by using a symmetric resistor ladder configuration where impedance remains constant regardless of gain setting. This equipotential design ensures that phase relationships between different gain states remain coherent, eliminating phase incoherence while maintaining dynamic performance
Solution Approach 2:
The patent incorporates feedback mechanisms where the resistor ladder network is designed to provide stable, predictable impedance characteristics that can be monitored and adjusted. This feedback approach ensures linearity is maintained across gain transitions, preventing phase incoherence while preserving dynamic performance
3Stability of the object's composition
If compensation circuits are implemented to limit phase variations, then phase stability is improved, but current consumption increases
Solution Approach 1:
The patent designs a self-regulating resistor ladder network that automatically maintains phase stability through its inherent impedance-matching properties. The circuit self-adjusts to maintain constant phase relationships without requiring external compensation circuits, thereby achieving phase stability without increased current consumption
Data Source
AI summary
Technologies are provided for variable gain amplifiers (VGAs). An example VGA includes a resistor ladder including resistor legs coupled to first and second resistors; first differential switches connected to the resistor ladder and second differential switches connected to output nodes, a transistor in each of the first differential switches being coupled to an first electrical line interconnecting the first resistors and a different transistor in each of the first differential switches being coupled to a second electrical line interconnecting the second resistors; third differential switches connected to the resistor ladder and fourth differential switches connected to the output nodes, a transistor in each of the third differential switches being coupled to the first electrical line and a different transistor in each of the fourth differential switches being coupled to the second electrical line; and a pair of transistors respectively connected to the first differential switches and the third differential switches.