Low VT Antifuse Device with Dual Gate Oxide
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current anti-fuse memory devices face challenges in manufacturing with standard CMOS processes, particularly in achieving low threshold voltage and high reliability, due to mask alignment errors and the need for specific LV transistor processes, which incurs significant redesign costs and affects the quality of thin gate oxides.
Innovation Solution
The solution involves forming anti-fuse memory cells with a thick gate oxide in a high voltage well and a thin gate oxide in the same well, allowing for a low threshold voltage without additional CMOS process steps, and using existing CMOS process steps for I/O and core transistors, thereby simplifying mask layout and reducing mask misalignment issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If anti-fuse devices are manufactured using standard CMOS process with LV transistor processes, then threshold voltage can be reduced, but mask alignment errors increase and manufacturing precision deteriorates
Solution Approach 1:
The patent divides the transistor structure into two distinct gate oxide regions: a thick gate oxide region for the access transistor and a thin gate oxide region for the anti-fuse device. This segmentation allows each region to be optimized independently - the thin gate oxide enables low threshold voltage for the anti-fuse while the thick gate oxide maintains high voltage tolerance for the access transistor, eliminating the need for separate LV transistor processes and reducing mask alignment requirements
Solution Approach 2:
The patent applies local quality by creating different gate oxide thicknesses at different locations within the same transistor structure. The thin gate oxide is localized to the anti-fuse device region where low threshold voltage is needed, while the thick gate oxide is localized to the access transistor region where high voltage tolerance is required. This local differentiation resolves the contradiction by providing tailored electrical characteristics to each functional region without requiring global process changes
2Reliability
If additional processing steps are added to achieve low threshold voltage, then threshold voltage control improves, but device complexity increases
Solution Approach 1:
The patent achieves multi-functionality by using a single transistor structure to perform both access transistor functions and anti-fuse device functions. The unified transistor design with selectively thinned gate oxide allows the same device to operate as a high voltage tolerant access transistor in one region and as a low threshold voltage anti-fuse device in another region, eliminating the need for separate LV transistor processes and reducing overall device complexity
Solution Approach 2:
The patent changes the gate oxide thickness parameter locally within the transistor structure to achieve different electrical characteristics. By thinning the gate oxide specifically in the anti-fuse device region while maintaining thick gate oxide in the access transistor region, the patent achieves low threshold voltage control without adding processing steps, as the thinning can be accomplished through standard photolithography and etching processes already part of the CMOS fabrication flow
3Reliability
If thin gate oxide is formed in separate LV transistor processes, then threshold voltage decreases, but manufacturing costs increase
Solution Approach 1:
The patent merges the access transistor and anti-fuse device into a single unified transistor structure, combining functions that previously required separate devices and processes. This merging allows both high voltage tolerance and low threshold voltage characteristics to be achieved within one device using standard CMOS processes, eliminating the need for costly separate LV transistor fabrication processes
Solution Approach 2:
The patent enables the anti-fuse device to self-generate the low threshold voltage condition through local gate oxide thinning within the standard CMOS process flow, without requiring external LV transistor process intervention. The thin gate oxide region naturally provides the low threshold voltage needed for anti-fuse operation as an inherent property of the structure, eliminating additional manufacturing costs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of anti-fuse memory cells with a low programmed threshold voltage, improved reliability, and reduced manufacturing costs by maintaining consistent characteristics across different CMOS process generations without requiring redesign.
Implementation Method 1
Anti-fuse device 12 is considered a gate dielectric breakdown based anti-fuse devices
Data Source
AI summary
A one time programmable memory cell having an anti-fuse device with a low threshold voltage independent of core circuit process manufacturing technology is presented. A two transistor memory cell having a pass transistor and an anti-fuse device, or a single transistor memory cell having a dual thickness gate oxide, are formed in a high voltage well that is formed for high voltage transistors. The threshold voltage of the anti-fuse device differs from the threshold voltages of any transistor in the core circuits of the memory device, but has a gate oxide thickness that is the same as a transistor in the core circuits. The pass transistor has a threshold voltage that differs from the threshold voltages of any transistor in the core circuits, and has a gate oxide thickness that differs from any transistor in the core circuits. The threshold voltage of the anti-fuse device is lowered by omitting some or all of the threshold adjustment implants that is used for high voltage transistors fabricated in the I/O circuits.