Lower Electrode Support Pattern for High-Capacitance Memory Cells
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving improved electrical characteristics and reliability, particularly in highly integrated memory devices where capacitance and dielectric constants are critical.
Innovation Solution
The semiconductor device incorporates a lower electrode structure with a first and second portion on the substrate and sidewalls, respectively, along with a support pattern and a dielectric layer. The second portion of the lower electrode structure includes niobium and fluorine, with optional oxygen or nitrogen, and the dielectric layer has a tetragonal structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integration density of semiconductor memory devices is increased, then productivity and performance are improved, but reliability and electrical characteristics deteriorate due to reduced capacitance
Solution Approach 1:
The patent transitions from planar capacitor structures to vertically stacked capacitor structures with multiple electrodes arranged in the vertical dimension. This allows increasing capacitance without expanding the horizontal footprint, thereby maintaining high integration density while improving electrical characteristics and reliability through enhanced capacitance values.
Solution Approach 2:
The patent employs composite material structures including dielectric layers with high dielectric constants combined with conductive electrode materials. This composite approach enables achieving higher capacitance in a compact volume, resolving the contradiction between maintaining small device size for high integration and ensuring sufficient capacitance for reliable operation.
2Reliability
If capacitance of capacitor is increased to improve reliability, then electrical characteristics are improved, but device complexity increases
Solution Approach 1:
The capacitor structure is segmented into multiple discrete electrode layers and dielectric layers stacked vertically. This segmentation allows each layer to be independently optimized and formed using sequential deposition processes, managing complexity through modular construction while achieving high total capacitance.
Solution Approach 2:
The patent implements a nested structure where multiple electrode layers are positioned within a vertical stack, with each electrode nested relative to others in the vertical dimension. This nesting approach increases capacitance by utilizing multiple interfaces within a compact vertical space without proportionally increasing lateral device complexity.
3Reliability
If dielectric constant of dielectric layer is increased to improve capacitance, then electrical characteristics are improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the dielectric parameter by selecting materials with inherently high dielectric constants. This material parameter change achieves high capacitance without requiring extreme precision in layer thickness control, as the high dielectric constant provides capacitance enhancement that is less sensitive to dimensional variations compared to lower dielectric constant materials.
Data Source
AI summary
A method of manufacturing a semiconductor device includes: forming electrode holes by etching a mold structure including a mold layer and a support layer which are stacked on a substrate; forming lower electrode pillars filling the electrode holes; etching a portion of the support layer between the lower electrode pillars to form a support pattern having a through-hole exposing a portion of a top surface of the mold layer; removing the mold layer through the through-hole to expose sidewalls of the lower electrode pillars; and selectively forming lower electrode patterns on the sidewalls and top surfaces of the lower electrode pillars.