Lower Gate Cap Insulation for Backside Contact Over-Etch
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Solution Overview
Problem
The formation of backside contacts in semiconductor devices can result in over-etching, leading to short-circuits between the backside contact and the gate, causing device failure.
Innovation Solution
A lower gate cap is formed early in the device fabrication, positioned between semiconductor nanosheet fin stacks and the shallow trench isolation (STI) structure, to prevent over-etching and short-circuits. The lower gate cap is made of a dielectric material distinct from the STI material, providing electrical insulation between the gate and the backside contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If backside contacts are formed by removing substrate and etching through backside dielectric layer, then electrical contact to source/drain structures is achieved, but over-etching may expose the underside of the gate causing short-circuit and device failure
Solution Approach 1:
A lower gate cap is formed before backside contact etching to establish a protective barrier in advance. This cap is deposited conformally over the gate structure and then planarized, creating a predefined etch stop layer that prevents over-etching during subsequent backside contact formation processes
Solution Approach 2:
The lower gate cap serves as an intermediary protective layer between the gate structure and the etching process. This intermediate layer absorbs the etching damage and prevents direct contact between the etchant and the gate underside, thereby preventing short-circuits while allowing the etching to proceed to expose backside contact regions
2Reliability
If a protective layer is added to prevent over-etching, then short-circuit prevention is improved, but device structure complexity increases
Solution Approach 1:
The lower gate cap formation is merged with existing gate fabrication steps. The cap material is deposited conformally over the gate during the same process sequence used to form gate dielectric and other gate structures, and subsequent planarization integrates with standard surface flattening processes, thereby adding protection without significantly increasing structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The lower gate cap effectively prevents short-circuits between the backside contacts and the gate, ensuring the reliability and integrity of the semiconductor device by maintaining electrical insulation and preventing over-etching.
Implementation Method 1
A lower gate cap electrically insulates the gate from the backside electrical contact and includes a first region of the lower gate cap that is in contact with a shallow trench isolation (STI) structure of the backside part
Data Source
AI summary
Semiconductor devices include an active part that includes a semiconductor channel and a gate stack. A frontside part includes a frontside electrical contact to the active part. A backside part includes a backside electrical contact to the active part. A lower gate cap electrically insulates the gate from the backside electrical contact and includes a first region of the lower gate cap that is in contact with a shallow trench isolation (STI) structure of the backside part and a second region of the lower gate cap that is in contact with a surface of the backside electrical contact.