Lower-Layer Thick Metal Routing for Long-Net RC Delay
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Solution Overview
Problem
The challenge in IC manufacturing is the increase in resistance of metal lines due to scaling down, which degrades IC performance, particularly in advanced technology nodes, as thinner lines lead to higher RC delay, necessitating thicker lines in upper metallization layers but increasing via counts and degrading benefits.
Innovation Solution
Designing and fabricating thicker metal lines in lower metallization layers to allow long nets to be routed on these layers, reducing resistance while minimizing the use of vias, thereby optimizing metal line width and spacing across multiple layers to balance routing density and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If metal lines are scaled down to increase integration density, then more components can be integrated into a given area, but resistance of metal lines increases and RC delay degrades
Solution Approach 1:
The patent applies local quality by making metal lines in lower metallization layers thicker than those in upper layers. Specifically, the first metal lines in the first metallization layer have a first line width, while the second metal lines in the second metallization layer have a second line width that is greater than the first line width. This non-uniform distribution of line widths optimizes the resistance characteristics locally in different layers, allowing long nets to be routed on thicker lower-layer lines to reduce RC delay while maintaining high integration density.
2Reliability
If thicker metal lines are used in upper metallization layers to reduce resistance, then RC delay decreases, but via counts increase and manufacturing complexity increases
Solution Approach 1:
The patent inverts the conventional approach by placing thicker metal lines in the lower metallization layer instead of the upper layer. The second metallization layer (upper) has metal lines with a greater line width, while the first metallization layer (lower) has metal lines with a smaller line width. This inversion allows long nets to be routed on the thicker upper-layer lines to reduce resistance and RC delay, while the routing strategy minimizes via counts by exploiting the lower via requirements of the lower layer for certain routing paths.
3Productivity
If metal line width is reduced to increase routing density, then more routes can be accommodated, but resistance increases and signal integrity degrades
Solution Approach 1:
The patent applies parameter changes by varying the line width parameter across different metallization layers. The first metal lines have a first line width and the second metal lines have a second line width that is greater than the first line width. This parameter variation allows the design to achieve both high routing density (by using thinner lines where needed) and good signal integrity (by using thicker lines for long nets in the upper layer), thereby resolving the contradiction between routing density and signal integrity.
Data Source
AI summary
An IC structure includes first, second, third, and fourth transistors on a substrate, a first net and a second net. The first net includes a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors. The second net includes a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors. A count of the first metal vias of the first net is less than a count of the second metal vias of the second net, and a line height of the first metal line of the first net is greater than a line height of the second metal line of the second net.