Lower Level Cache Line Testing via Burst Access
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Solution Overview
Problem
Modern processors face reliability issues due to process variations and circuit aging, particularly in lower level caches like L2 and L3, which are more susceptible to imperfections and require effective stress testing to ensure safe operation, especially as CMOS designs become less reliable with shrinking process technology.
Innovation Solution
A software-based mechanism that systematically targets specific cache lines in lower level caches through burst accesses, bypassing the L1 cache to perform targeted testing, allowing for adaptive online detection and disabling of weak lines, especially in the Near Threshold Computing range for low power operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If lower level caches (L2, L3) are used to increase processing capacity, then productivity is improved, but reliability deteriorates due to susceptibility to process variations and circuit aging
Solution Approach 1:
The patent segments the cache testing process into targeted bursts that systematically exercise specific cache lines in lower level caches. By dividing the cache into addressable lines and applying stress tests to specific segments, the system can identify and isolate weak lines without compromising the entire cache structure, thus maintaining reliability while preserving processing capacity.
Solution Approach 2:
The patent performs preliminary stress testing on cache lines before they are fully utilized in normal operation. By conducting burst accesses and validity checks in advance, the system identifies potentially weak cache lines early, allowing for preventive measures such as disabling affected lines before they cause reliability failures during actual processing.
2Reliability
If hardware mechanisms are added to test lower level caches, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements a self-service testing mechanism where the processor uses its own existing hardware resources (cache controllers, memory interfaces) to perform stress tests on lower level caches. Instead of adding dedicated test hardware, the system leverages normal cache access paths and control logic to execute test sequences, thereby improving reliability without increasing device complexity.
Solution Approach 2:
The patent makes existing cache hardware multi-functional by enabling it to perform both normal data processing and stress testing operations. The same cache controllers and access paths used for regular operations are repurposed to execute test sequences, allowing a single hardware structure to serve multiple functions and eliminate the need for separate testing infrastructure.
3Reliability
If L1 cache is used for all accesses, then reliability is improved, but productivity decreases due to limited capacity
Solution Approach 1:
The patent implements dynamic cache access patterns that adaptively route accesses based on the operational phase. During normal operation, the system dynamically utilizes lower level caches (L2, L3) to increase throughput. During designated test phases, it dynamically redirects accesses to stress specific cache lines in lower level caches. This dynamic switching allows the system to maintain high productivity while periodically ensuring reliability through targeted testing.
Data Source
AI summary
A first threshold number of cache lines may be fetched to populate each of the ways of a first cache set of a higher level cache and each of the ways of a first cache set of a lower level cache. A second threshold number of cache lines may be fetched to map to the first cache set of the higher level cache and a second cache set of the lower level cache. The first threshold number of cache lines may be accessed from the second from the first cache set of the lower level cache.