Lower Metal Layer Intercell Routing for IC Signal Delay Reduction

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Solution Overview

Problem

The use of high-resistive metal vias in integrated circuits for intercell routing leads to signal delays, increased power consumption, and routing congestion, limiting the maximum operating frequency and requiring larger IC footprints.

Innovation Solution

The implementation of intercell metal interconnects that extend entirely on lower metal layers, such as M1, to directly connect nodes between IC cells without using high-resistive vias, allowing for simpler and less resistive electrical routing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-generated harmful factors

If higher metallization layers (M3 or higher) are used for intercell routing, then routing congestion is reduced and signal crosstalk is minimized, but metal via resistance increases leading to higher power consumption and signal delays

Engineering Contradiction:

Improvesignal crosstalkVSAvoidpower consumption

Core Design Contradiction:

Object-generated harmful factorsVSLoss of energy

Solution Approach 1:

The patent transitions from using higher metal layers (M3 or above) for intercell routing to utilizing lower metal layers (M1 or M2) that are closer to the silicon substrate. This dimensional change in the metallization stack enables direct routing through lower layers, eliminating the need for multiple via transitions and reducing both power consumption and signal delays while maintaining effective crosstalk management through optimized routing geometry

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If higher metallization layers are used for intercell routing, then routing paths are more available, but metal via resistance causes increased signal delays and limits maximum operating frequency

Engineering Contradiction:

Improverouting availabilityVSAvoidsignal speed

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

Instead of the conventional approach of using higher metal layers to avoid routing congestion, the patent inverts the strategy by utilizing lower metal layers (M1/M2) for intercell routing. This inversion eliminates the need for high-resistance via transitions, thereby improving signal speed and maximum operating frequency while routing availability is maintained through optimized track allocation and cell design

Inventive Principle:

Principle #13The other way round (Inversion)

3Adaptability or versatility

If higher metallization layers are used for intercell routing, then routing flexibility is improved, but the IC footprint increases due to routing congestion

Engineering Contradiction:

Improverouting flexibilityVSAvoidIC footprint

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent utilizes lower metal layers (M1/M2) for intercell routing, changing the dimensional approach from upper-layer routing to lower-layer routing. This enables more efficient space utilization within the IC, reducing the overall footprint required for routing while maintaining flexibility through optimized track reservation and cell-to-cell direct connections

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11538757B2Integrated circuit with circuit cells having lower intercell routing metal layers

Publication Date: 2022.12.27 QUALCOMM INC

AI summary

An integrated circuit (IC) including an IC cell arranged in a row of IC cells, wherein the IC cells in the row have substantially the same height, wherein the IC cell includes a portion of an intercell metal interconnect terminating at the IC cell at a metal layer or extending entirely through the IC cell on the metal layer and electrically connecting together a pair of nodes of a pair of IC cells, respectively.