Display Lower Metal Line Layout to Reduce Gate-Layer Interference
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing display devices face challenges in optimizing the layout of lower metal lines and gate layers to enhance display performance and reduce interference, particularly in non-display areas.
Innovation Solution
The display device incorporates a lower metal line that surrounds the display area and does not overlap with the gate layer in the non-display area, ensuring efficient electrical connections and minimizing interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the lower metal line is disposed to surround the display area in the non-display area, then the electrical connection efficiency is improved, but the interference with the gate layer increases
Solution Approach 1:
The patent resolves the contradiction by utilizing the vertical dimension (thickness direction) to separate the lower metal line from the gate layer. The lower metal line is positioned in a lower layer while the gate layer is in an upper layer, allowing the metal line to surround the display area for efficient electrical connection without overlapping with the gate layer in the plan view, thus eliminating electrical interference.
Solution Approach 2:
The patent applies nesting by placing the lower metal line within a structural framework that does not interfere with the gate layer. The metal line is nested in a lower positional layer while the gate layer occupies an upper positional layer, allowing both components to coexist without overlap in the horizontal plane while maintaining their respective functions.
2Productivity
If the lower metal line overlaps the channel of the driving transistor, then the electrical connection is enhanced, but the reliability of the thin film transistor decreases
Solution Approach 1:
The patent resolves this contradiction by transitioning to a vertical arrangement where the lower metal line and the driving transistor channel are separated in the thickness direction. The metal line is positioned in a lower layer while the channel is in an upper layer, allowing electrical connection enhancement without compromising transistor reliability through overlap.
Solution Approach 2:
The patent extracts the lower metal line from the same horizontal plane as the transistor channels by positioning it in a separate vertical layer. This extraction eliminates the harmful overlap between the metal line and the channels of both driving and switching transistors, thereby maintaining transistor reliability while preserving electrical connection functionality.
3Reliability
If the lower metal line is positioned close to the display area, then the display performance is improved, but the interference with transistor channels increases
Solution Approach 1:
The patent resolves this contradiction by utilizing the vertical dimension to separate the lower metal line from the transistor channels. The metal line is positioned in a lower layer close to the display area for improved display performance, while the channels are positioned in upper layers, eliminating horizontal overlap and interference between the metal line and transistor components.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A display device includes a display area including a plurality of pixels and a non-display area located around the display area. The display device further includes a base substrate, a lower metal line disposed on the base substrate and surrounding at least a portion of the display area in a plan view, and a gate layer disposed on the lower metal line. In the non-display area, the lower metal line does not overlap the gate layer.