Lowered Epitaxial Source/Drain Regions for Low-Resistance Scaling
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Solution Overview
Problem
As minimum feature size reduces in semiconductor devices, issues such as leakage, parasitic devices, and resistance degradation occur, necessitating a solution to improve integration density and reduce channel resistance and source/drain contact resistance.
Innovation Solution
The semiconductor device incorporates lowered epitaxial source/drain regions with a buried epitaxial layer, extending below the substrate surface, increasing volume and introducing compressive stress to enhance channel mobility and reduce resistance, while using sidewall spacers for electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to improve integration density, then more components can be integrated into a given chip area, but leakage and parasitic devices occur
Solution Approach 1:
The patent extends source/drain regions vertically below the substrate surface into a second dimension, creating lowered epitaxial source/drain regions. This dimensional change increases the effective volume of source/drain regions without increasing planar footprint, thereby improving integration density while providing sufficient contact area to maintain low resistance and reduce leakage effects.
Solution Approach 2:
The patent performs preliminary epitaxial growth to form lowered source/drain regions before final device fabrication steps. By pre-forming these extended regions with appropriate doping profiles and geometries, the design anticipates and prevents leakage and parasitic device formation that would otherwise occur at scaled dimensions.
2Productivity
If minimum feature size is reduced to improve integration density, then more components can be integrated into a given chip area, but resistance degradation occurs
Solution Approach 1:
The patent extends source/drain regions vertically below the substrate surface, increasing their volume and cross-sectional area for current flow. This dimensional extension compensates for resistance increases that would normally occur when feature sizes are reduced, maintaining low contact resistance while enabling higher integration density.
Solution Approach 2:
The patent changes the geometric parameters of source/drain regions by extending them downward below the substrate surface. This parameter change increases the effective contact area and volume, thereby reducing contact resistance and channel resistance degradation that typically accompany feature size reduction for improved integration density.
3Reliability
If epitaxial source/drain regions are lowered to increase volume and reduce resistance, then channel resistance and contact resistance are reduced, but device structure becomes more complex
Solution Approach 1:
The patent segments the epitaxial growth process into distinct stages: forming the lowered source/drain regions below the substrate surface, then forming the channel and gate structures above. This segmentation allows each region to be optimized independently while maintaining a relatively simple overall structure that achieves reduced resistance without excessive complexity.
4Reliability
If epitaxial source/drain regions are lowered to enhance channel mobility, then device performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary epitaxial growth to form lowered source/drain regions with precise doping profiles and geometries before subsequent fabrication steps. By establishing the correct structure and composition early in the process, manufacturing precision is optimized while achieving the desired mobility enhancement through controlled stress introduction.
Solution Approach 2:
The patent carefully controls epitaxial growth parameters (temperature, pressure, doping rates, gas flows) to achieve the desired lowered source/drain region geometry and composition. These parameter changes enable precise control over the stress state and crystal structure, enhancing channel mobility while managing manufacturing precision requirements through optimized process conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces channel resistance and contact resistance, improving mobility and process uniformity, thereby enhancing device performance and integration density.
Implementation Method 1
increasing volume and introducing compressive stress to enhance channel mobility and reduce resistance
Data Source
AI summary
Embodiments of the present disclosure relate to a semiconductor device with lowered source/drain regions to reduce channel resistance (Rch) and source/drain contact resistance loading.