Low-k ILD Cap Layer for Gate Height Control
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Solution Overview
Problem
In semiconductor fabrication at the 10 nm technology node and beyond, significant ILD dishing occurs during gate oxide etching and metal gate recessing, leading to excessive polysilicon dummy gate height requirements due to selectivity issues and material loss.
Innovation Solution
Implementing a low-k ILD cap layer, specifically composed of silicon oxycarbonitride (SiOCN) or silicon oxycarbide (SiOC), to prevent ILD dishing by forming it over the entire substrate and in recesses between polysilicon gates, thereby reducing material loss and improving gate height control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional HDP oxide is used as ILD without cap layer, then process simplicity is maintained, but significant ILD dishing occurs (32 nm loss) requiring increased gate height budget
Solution Approach 1:
A low-k ILD cap layer is deposited over the HDP oxide ILD before subsequent processing steps. This preliminary action protects the ILD from dishing during gate oxide etching and metal gate recessing, preventing the loss of 32 nm ILD material that would otherwise occur.
Solution Approach 2:
The low-k ILD cap layer acts as an intermediary protective layer between the processing steps (etching and recessing) and the HDP oxide ILD. It absorbs the mechanical stress and prevents direct damage to the ILD, thereby maintaining ILD flatness without complicating the overall process flow.
2Manufacturing precision
If thicker polysilicon dummy gate is used to compensate ILD dishing loss, then gate height budget is satisfied, but device complexity and fabrication difficulty increase
Solution Approach 1:
The low-k ILD cap layer is deposited beforehand to prevent ILD dishing, thereby preserving the original ILD thickness. This eliminates the need to add 32 nm to the polysilicon dummy gate height, allowing use of thinner, more manageable gate structures with better control.
Solution Approach 2:
The patent converts the potential harm of adding complex thick dummy gate structures into a benefit by using the low-k ILD cap layer. This cap layer not only prevents ILD dishing but also reduces micro-loading effects, simultaneously improving gate height control while simplifying the overall device structure.
3Productivity
If conventional oxide etching and metal gate recessing are performed without protective cap, then processing speed is maintained, but 32 nm of ILD material is lost to dishing
Solution Approach 1:
The low-k ILD cap layer is deposited in advance before the oxide etching and metal gate recessing steps. This preliminary protective layer prevents the loss of 32 nm ILD material during these processing steps while allowing the processes to proceed at normal speed without additional complexity.
Solution Approach 2:
The low-k ILD cap layer provides beforehand cushioning protection to the HDP oxide ILD during subsequent processing. It absorbs the mechanical stress and material loss that would otherwise directly affect the ILD, preventing 32 nm of material loss while maintaining processing efficiency.
4Manufacturing precision
If low-k ILD cap layer is deposited to prevent ILD dishing, then ILD flatness is improved and gate height budget is reduced, but additional processing step is added
Solution Approach 1:
The low-k ILD cap layer is deposited as a preliminary step before gate oxide etching and metal gate recessing. This single additional step prevents 32 nm of ILD material loss and eliminates the need for thicker dummy gates, thereby improving ILD flatness and reducing gate height budget requirements.
Solution Approach 2:
The patent converts the apparent harm of adding a processing step into a benefit. The low-k ILD cap layer deposition not only prevents ILD dishing but also reduces micro-loading effects, simultaneously improving manufacturing precision while the added step remains manageable within the overall process flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The low-k ILD cap layer effectively minimizes gate height budget requirements by preventing ILD dishing, reducing micro-loading, and enhancing gate height control, resulting in a 20 nm reduction in gate height budget compared to conventional processes.
Implementation Method 1
forming an ILD cap layer in the recess between the adjacent polysilicon gates
Implementation Method 2
planarizing the ILD cap layer down to an upper surface of the adjacent polysilicon gates
Implementation Method 3
removing the polysilicon from the polysilicon gates to expose a gate oxide at a bottom of each gate opening by RIE
Data Source
AI summary
A method for eliminating interlayer dielectric (ILD) dishing and controlling gate height uniformity is provided. Embodiments include forming a plurality of polysilicon gates over a substrate, each gate having spacers formed on sides of the polysilicon gates and a nitride cap formed on an upper surface; forming a gapfill material between adjacent polysilicon gates; forming an oxide over the gapfill material between the adjacent polysilicon gates; removing the nitride caps; removing a portion of the oxide between the adjacent polysilicon gates, forming a recess; and forming an ILD cap layer in the recess between the adjacent polysilicon gates.