LP-SSIC Inter-Chip Communications for High Throughput Low Power

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

USB High Speed Inter-Chip (HSIC) specifications are insufficient for next-generation devices requiring higher data rates, such as 802.11ac and 802.11ad, due to limited throughput and increased power consumption, especially in devices with multiple peripherals.

Innovation Solution

Implementing low power SuperSpeed inter-chip (LP-SSIC) communications using USB3.0 interface within computing devices, which enables higher bitrates while reducing power consumption by modifying physical, link, and protocol layer parameters, and utilizing scalable low voltage signaling and optimized interconnects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If USB HSIC is used for internal communications, then USB2.0 based communication is enabled, but data throughput is limited to 480 Mbps

Engineering Contradiction:
Improvedata throughputVSAvoidfuture scalability
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent changes the physical layer parameters by transitioning from USB2.0 HSIC (480 Mbps) to USB3.0 SuperSpeed (5 Gbps), modifying the signaling rate and physical interface characteristics to achieve higher throughput while maintaining USB protocol compatibility

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If USB2.0 architecture is used with multiple devices, then device compatibility is maintained, but power consumption increases

Engineering Contradiction:
Improvedevice compatibilityVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent applies local quality by implementing USB3.0 SuperSpeed interface specifically for internal inter-chip communications while maintaining USB2.0 compatibility for external peripheral connections, optimizing power consumption for the internal high-speed path without affecting external device compatibility

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS8719475B2Method and system for utilizing low power superspeed inter-chip (LP-SSIC) communications
Publication Date: 2014.05.06 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US8719475B2 patent drawing
  • US8719475B2 patent drawing
  • US8719475B2 patent drawing

AI summary

Inter-chip connectivity may be provided in a computing device, which may comprise a USB host and at and at least one USB device embedded within the computing device, based on Universal Serial Bus version 3.0 (USB3.0) interface. In this regard, internal communication of data between the USB host and embedded USB device may be performed via USB3.0 SuperSpeed signals. The USB host and/or the USB3.0 interface may be configured to enable USB3.0 internal communication of data, and to reduce power consumption during the internal communication of data compared to external USB3.0 communications. Configuration of the USB3.0 interface for internal communication of data may comprises modifying and/or adjusting physical (PHY) layer, link layer, and/or protocol layer related parameters, functions, resources, and/or operations. The USB3.0 SuperSpeed signals may be communication using scalable low voltage signaling (SLVS). In this regard, Input/Output (IO) Swing may be set based on loopback training sequence.