Concatenated LPAC Coding With Outer Block Codes for Stable Decoding
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Solution Overview
Problem
Polarization adjusted convolutional (PAC) codes face challenges in practical utility due to variability in computational complexity, limited throughput, and the need for extreme low frame error rates (FER) in applications like fiber-optic data transmission and hard-disk storage, which existing technologies struggle to address effectively.
Innovation Solution
A concatenated coding scheme employing PAC codes as inner codes, utilizing a layered structure and customized outer codes to mitigate computational variability and enhance throughput, with a focus on generalized concatenated coding (GCC) and multi-level coding (MLC) techniques to achieve low FER and scalable throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential decoding is used for PAC codes, then near-optimal FER performance is achieved, but computational complexity variability becomes highly sensitive to noise severity
Solution Approach 1:
The patent segments the sequential decoding process into multiple parallel decoding paths or stages, dividing the computational workload to reduce variability in complexity while maintaining the near-optimal FER performance achieved by sequential decoding
2Reliability
If PAC codes are decoded sequentially to exploit channel polarization benefits, then decoding accuracy is improved, but throughput is severely limited
Solution Approach 1:
The patent introduces parallelism in the decoding architecture by processing multiple code blocks or decoding stages simultaneously across different computational units, effectively adding a temporal or spatial dimension to overcome the sequential bottleneck while preserving the polarization benefits
3Productivity
If pipelining and unrolling techniques are used to improve PAC decoder throughput, then processing speed is increased, but chip area and cost increase due to extra memory requirements
Solution Approach 1:
The patent optimizes the memory architecture by changing parameters such as memory organization, cache utilization, or memory access patterns to reduce the total memory capacity required for pipelining and unrolling operations, thereby improving throughput without proportionally increasing chip area
4Productivity
If increased clock speeds are used to increase throughput, then processing capacity is improved, but power-density problems arise in VLSI circuits
Solution Approach 1:
The patent employs dynamic voltage and frequency scaling or adaptive clock gating techniques that adjust the operating frequency and power consumption dynamically based on workload demands, allowing throughput to be increased when needed while minimizing power density under normal operating conditions
Data Source
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AI summary
An encoder 102 receives a concatenated encoder input block d, splits d into an outer code input array a, and encodes a using outer codes to generate an outer code output array b. The encoder generates, from b, a concatenated code output array x using a layered polarization adjusted convolutional (LPAC) code. A decoder 106 counts layers and carries out an inner decoding operation for a layered polarization adjusted convolutional (LPAC) code to generate an inner decoder decision: Formula (I) from a concatenated decoder input array y and a cumulative decision feedback (Formula (IV)). The decoder carries out an outer decoding operation to generate from Formula (I) an outer decoder decision â i and carries out a reencoding operation to generate a decision feedback Formula (II) from â i where the number of layers is an integer greater than one, with a concatenated decoder output block Formula (III) being generated from outer decoder decisions.