Serial LPCK Decoding for CXL Memory Transfer Block Error Recovery
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Solution Overview
Problem
Existing memory devices, particularly those using the Compute Express Link (CXL) standard, face challenges in efficiently correcting errors during reading and writing operations.
Innovation Solution
The implementation of a low power chip kill (LPCK) system that utilizes a combination of cyclic redundancy check (CRC), error correction code (ECC), and low power chip kill (LPCK) encoders and decoders to detect and correct errors in memory transfer blocks, employing both binary and non-binary Hamming codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction techniques are used in memory devices, then data reliability is improved, but power consumption increases
Solution Approach 1:
The patent applies partial action by implementing error correction only when necessary - using CRC checks to identify errors and then applying ECC decoding only to correctable error patterns. This avoids the excessive power consumption of continuous full ECC processing while maintaining data reliability for actual error cases.
Solution Approach 2:
The memory system performs self-diagnosis through CRC validation and self-correction through iterative ECC decoding. The system automatically detects errors via CRC, determines correctability, and applies correction without external intervention, reducing the need for additional power-consuming external error handling mechanisms.
2Reliability
If iterative error correction decoding is performed, then error correction capability is improved, but processing time increases
Solution Approach 1:
The patent performs preliminary CRC validation before initiating iterative ECC decoding. This preliminary check quickly identifies whether errors exist and whether they are potentially correctable, avoiding unnecessary iterative decoding processing time for error-free or uncorrectable cases while maintaining full correction capability when needed.
Solution Approach 2:
The system skips iterative decoding when CRC indicates no errors or when error patterns are determined to be uncorrectable. This selective approach rushes through the processing pipeline for cases where full iterative correction is unnecessary, significantly reducing average processing time while maintaining correction capability for valid cases.
3Reliability
If multiple encoding schemes (CRC, ECC, LPCK) are implemented, then error detection and correction capability is improved, but device complexity increases
Solution Approach 1:
The patent segments the error handling function into distinct modular components: CRC encoder/decoder for error detection, ECC encoder/decoder for error correction, and LPCK encoder/decoder for additional protection. Each module operates independently with clearly defined interfaces, making the complex system manageable and maintainable while achieving comprehensive error handling capability.
Solution Approach 2:
The memory system implements multi-functional error handling where the same hardware infrastructure supports multiple encoding schemes (CRC, ECC, LPCK) and multiple operation modes (encoding, decoding, validation, correction). This universal approach consolidates what could be separate complex systems into a unified error management architecture.
Data Source
AI summary
A system and method for memory error detection and recovery in a decoding system in CXL components is presented. The method includes receiving, into a first decoder within the decoding system, a memory transfer block (MTB) having data and parity information, and having a vertical portion and a horizontal portion, performing error detection and correction on the vertical portion of the MTB using binary hamming code logic within the first decoder; and upon performing error detection and correction in the first decoder, then forwarding MTB to a second decoder, and performing error detection and correction, via the second decoder, on the horizontal portion of the MTB using a non-binary hamming code logic within the second decoder such that the first and second decoders perform the error detection and correction on the vertical and horizontal portions of the MTB in a serial manner.