Command Bus Training Mode for Faster LPDDR CA Calibration
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Solution Overview
Problem
The existing command bus training methods for LPDDR4 and LPDDR5 memory devices are slow and require significant firmware coordination, limiting the speed and quality of command bus training due to the need for iterative testing of command/address values, which can miss thousands of potential sampling points for observing correctness or errors.
Innovation Solution
The implementation of a command address training mode (CATM) similar to that used in DDR5 memory devices, which simplifies error checking by returning a parity value instead of actual sampled values, reducing the coordination work required for firmware and enabling faster and more efficient command bus training.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional command bus training methods are used for LPDDR4 and LPDDR5 memory devices, then iterative testing of command/address values can be performed, but the training process becomes slow and requires significant firmware coordination, missing thousands of potential sampling points
Solution Approach 1:
The patent applies the CATM mode from DDR5 memory devices to LPDDR4 and LPDDR5 devices, creating a copied training mechanism that returns parity values instead of actual sampled values. This copying of the DDR5 approach enables faster training by reducing firmware coordination overhead while maintaining sufficient training accuracy through parity-based error checking.
2Reliability
If actual sampled CA pattern values are returned during command bus training, then complete sampling data is available for error checking, but the coordination work required from firmware increases significantly
Solution Approach 1:
The patent extracts only the essential error checking information (parity values) from the complete sampled CA pattern data, removing the unnecessary transmission of full sampled values. This extraction approach maintains reliability by detecting sampling errors through parity checks while dramatically reducing firmware coordination complexity.
Solution Approach 2:
Instead of returning actual sampled values and having firmware perform error checking, the patent inverts the approach by having the memory device compute and return only parity values, with the memory controller then performing the error checking based on these compressed parity results.
3Adaptability or versatility
If command bus training is performed using existing LPDDR4/LPDDR5 methods, then standardization is maintained, but the training process is limited by slow iterative testing and firmware coordination requirements
Solution Approach 1:
The patent makes the CATM training mode universal by applying it across multiple memory device types (LPDDR4, LPDDR5, and DDR5), enabling a single standardized fast training approach to work across different memory technologies. This multi-functionality reduces training time while maintaining broad compatibility through standardized parity-based error checking.
Data Source
AI summary
Techniques for command bus training to a memory device includes triggering a memory device to enter a first or a second command bus training mode, outputting a command/address (CA) pattern via a command bus and compressing a sampled CA pattern returned from the memory device based on whether the memory device was triggered to be in the first or the second command bus training mode.