LPDDR Memory Pattern Generation for CA Signal Control
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Solution Overview
Problem
LPDDR memory systems face challenges in accurately controlling command/address (CA) signal lines during training, testing, and verification processes due to limitations in mapping relationships between physical addresses and memory components, leading to unreliable results.
Innovation Solution
A method is introduced to preset mapping relationships between physical addresses and memory components, generate a command truth value table, and determine values for rows, columns, and banks based on this table to create a pattern that accurately controls CA signal lines, enhancing the reliability of training, testing, and verification processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If Memory Controller is used for training, testing and verifying LPDDR, then the process can be automated, but accurate control of CA signal lines cannot be achieved
Solution Approach 1:
The patent introduces an external pattern generator as an intermediary device between the test system and the LPDDR memory. This pattern generator produces command/address signals with precise control over CA signal lines, acting as a mediator that bridges the automation capability of computer-controlled systems with the precise signal control requirements of memory testing. The pattern generator translates automated test sequences into accurately timed and sequenced memory commands.
2Device complexity
If conventional mapping relationships are used between physical address and memory components, then the system structure is simple, but the control accuracy of CA signal lines is insufficient
Solution Approach 1:
The patent segments the physical address into multiple distinct components with specific bit assignments: bank address (bits 7-4), column address (bits 11-8), and row address (bits 15-12). This segmentation allows each component to be independently controlled and mapped to specific CA signal lines, enabling precise control of memory addressing sequences while maintaining a structured and manageable mapping relationship.
Solution Approach 2:
The patent applies different mapping rules to different segments of the address space. Specifically, it assigns particular bits of the physical address to specific memory components (bank, column, row) based on the required CA signal sequence. This local differentiation in mapping quality ensures that each segment of the address space is optimized for its specific control requirements, achieving precise CA signal line control through targeted bit assignments.
Data Source
AI summary
The present disclosure relates to a method for generating a pattern of a memory, a computer-readable storage medium and a computer device, the method for generating a pattern of a memory includes: presetting mapping relationships between a physical address and a row, a column and a bank, and determining bits of the physical address corresponding to the row, the column and the bank; taking a preset number of values as setting data, the preset number being the same as a number of signal address lines in the memory; obtaining a command truth value table, which is used to define relationships between bits of the physical address and commands; determining values of the row, the column and the bank based on the command truth value table and the setting data; generating the pattern based on the values of the row, the column and the bank and the mapping relationships.