LPDDR Nonvolatile Memory Test Operation via Dedicated CA Pins
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Solution Overview
Problem
The existing LPDDR nonvolatile memory devices face data collision issues during test operations due to the transmission of command signals and addresses through shared pins, limiting the usage of test equipment and increasing test time and costs.
Innovation Solution
A nonvolatile memory device design that transmits command signals and addresses directly through CA pins in a test mode, bypassing the overlay window to prevent data collision, utilizing a command decoder and address decoder to manage signals and addresses independently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If command signals and addresses are transmitted through shared data pins in overlay window mode, then the LPDDR nonvolatile memory device can perform embedded operations, but data collision occurs during test operations and test time increases
Solution Approach 1:
The patent segments the signal transmission paths by separating command/address signal transmission from data transmission. During test operations, command signals and addresses are transmitted through dedicated CA pins rather than sharing data pins, thereby preventing data collision while maintaining embedded operation capability through the overlay window mechanism.
2Adaptability or versatility
If command signals and addresses are transmitted through shared data pins, then the device supports LPDDRx interface standards, but test equipment usage is limited and test costs increase
Solution Approach 1:
The patent implements dynamic pin assignment where the function of pins changes based on operation mode. During normal embedded operations, data pins are used for command and address transmission through the overlay window. During test operations, the system dynamically switches to use dedicated CA pins for command/address transmission, enabling compatibility with conventional test equipment while maintaining interface standard compliance.
3Adaptability or versatility
If the overlay window is used for command and address transmission, then embedded operations are enabled, but data collision occurs with address driving units
Solution Approach 1:
The patent introduces dedicated CA pins as intermediary transmission paths for command signals and addresses during test operations. This intermediary path bypasses the data pins used by address driving units, eliminating the data collision problem while preserving the overlay window's embedded operation functionality. The CA pins serve as a mediator that separates conflicting signal paths.
Data Source
AI summary
A nonvolatile memory device is provided relating to a test operation for a Low Power Double-Data-Rate (LPDDR) nonvolatile memory device. The nonvolatile memory device comprises a command decoder configured to decode a test mode signal in a test mode to output program and erasure signals into a memory, an address decoder configured to decode a command address inputted through an address pin in the test mode to output a cell array address into the memory, and an overlay window configured to store a data inputted through a data pin in the test mode.