LPDDR Power Network Layout for Narrower Supply Lines
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Solution Overview
Problem
Conventional power management circuits in low-power double data rate memories have large power supply line widths, leading to increased circuit area and slowed speed, as well as significant power consumption and leakage current during standby mode.
Innovation Solution
A power management circuit utilizing a low dropout regulator and power network structure with a reduced line width, where the first voltage is used as an external power supply to generate a second voltage, and a control signal is used to adjust voltage differences and reduce power consumption and leakage current in standby mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the line width of the power supply is increased to reduce resistance, then the resistance is reduced, but the circuit area is increased and speed is slowed down
Solution Approach 1:
The power supply line is segmented into multiple narrower lines arranged in parallel, replacing a single wide line. This segmentation reduces the area occupied by the power supply line while maintaining low resistance through parallel conduction paths, thereby preserving signal speed without increasing circuit area.
Solution Approach 2:
The power supply lines are arranged in a three-dimensional stacked configuration rather than a single planar layer. This vertical stacking reduces the planar area occupied by power supply lines while providing multiple conduction paths that maintain low resistance, thus improving signal speed without increasing overall circuit area.
2Reliability
If the line width of the power supply is increased to reduce resistance, then the resistance is reduced, but the circuit area is increased
Solution Approach 1:
The power supply line is segmented into multiple narrower lines arranged in parallel, replacing a single wide line. This segmentation reduces the area occupied by the power supply line while maintaining low resistance through parallel conduction paths, thereby preserving signal speed without increasing circuit area.
Solution Approach 2:
The power supply lines are arranged in a three-dimensional stacked configuration rather than a single planar layer. This vertical stacking reduces the planar area occupied by power supply lines while providing multiple conduction paths that maintain low resistance, thus improving signal speed without increasing overall circuit area.
3Reliability
If voltage VDD1 is used during standby mode, then power supply is maintained, but power consumption and leakage current increase
Solution Approach 1:
The power management circuit dynamically switches between different power supply voltages based on operational mode. During standby mode, it transitions from full power supply (VDD1) to a reduced voltage state, minimizing power consumption and leakage current while maintaining sufficient power supply stability for essential functions. During active mode, it restores full power supply for complete performance.
Solution Approach 2:
The power management circuit changes the voltage parameter of the power supply based on operational requirements. During standby mode, it reduces the voltage parameter from VDD1 to a lower voltage level, significantly reducing power consumption and leakage current while maintaining adequate power supply stability for maintaining memory state. During active mode, it restores the voltage parameter to VDD1 for full performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces power supply line width, saving power consumption and leakage current, with the line width reduced by 81% and effective power management during standby mode.
Implementation Method 1
the low dropout regulator adjusts a voltage difference between the first voltage and the second voltage according to the reference voltage
Data Source
AI summary
A power management circuit in a low-power double data rate memory is configured to manage a plurality of power supplies memory according to a reference voltage. A low dropout regulator has a first transmitting terminal and a second transmitting terminal. The low dropout regulator adjusts a voltage difference between a first voltage and a second voltage according to the reference voltage. A power network structure is electrically connected to the low dropout regulator. A first power network circuit has a first connecting point, a grid shape and a first unit network space. A second power network circuit has a second connecting point, another grid shape and a second unit network space. The second connecting point is separated from the first connecting point by a distance. The distance is smaller than or equal to one of the first unit network space and the second unit network space.