LPDDR Multi-Chip ZQ Calibration with Master-Slave Looping
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Solution Overview
Problem
The increasing demand for LPDDR capacity necessitates more chips to be placed in a package, but the reduced number of ZQ calibration resistors in LPDDR5 requires individual ZQ calibration, posing a challenge for efficient impedance matching across multiple chips.
Innovation Solution
A single-loop and double-loop memory device design allows multiple chips to share a ZQ calibration resistor through a master-slave configuration, where a master chip initiates calibration and cascaded slave chips follow, using a control circuit to synchronize the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more chips are placed in one LPDDR package to increase capacity, then the memory capacity increases, but the number of ZQ calibration resistors becomes insufficient for individual calibration of each chip
Solution Approach 1:
The calibration process is segmented into multiple phases where chips are calibrated in different time slots. The memory device divides the calibration timeline into segments, allowing each chip to perform ZQ calibration sequentially during its assigned time slot, thus enabling individual calibration despite having fewer physical resistors.
Solution Approach 2:
The memory device performs preliminary configuration by assigning specific time slots to each chip for calibration. Before actual calibration begins, the system pre-arranges the calibration schedule and configures the multiplexer to route the shared ZQ resistor to the appropriate chip at the appropriate time, ensuring organized sequential calibration.
2Measurement precision
If each chip performs individual ZQ calibration, then the impedance matching accuracy improves, but the calibration time and complexity increase significantly
Solution Approach 1:
Multiple chips share a single ZQ calibration resistor through time-division multiplexing. The system merges the calibration resources of multiple chips into one shared resistor by carefully controlling the timing and routing, allowing sequential access to the same calibration resource without requiring separate resistors for each chip.
Solution Approach 2:
The calibration process uses periodic time-division multiplexing where each chip is assigned a specific periodic time slot for calibration. The multiplexer switches between chips in a periodic manner, enabling each chip to access the shared ZQ resistor at regular intervals throughout the calibration phase, thus reducing overall calibration time compared to completely sequential calibration.
3Device complexity
If a shared ZQ calibration resistor is used for multiple chips, then the device complexity and component count reduce, but the control and synchronization difficulty increases
Solution Approach 1:
The single ZQ calibration resistor serves multiple functions by being shared among multiple chips through time-division multiplexing. The same physical resistor performs calibration for different chips at different times, making the calibration resource universal and multi-functional, thus reducing the total component count while maintaining calibration capability for all chips.
Solution Approach 2:
A multiplexer acts as an intermediary between the shared ZQ resistor and multiple chips. The multiplexer mediates the connection, routing the calibration signal to the appropriate chip at the appropriate time based on control signals. This intermediary component simplifies the control logic by providing a centralized switching mechanism rather than requiring complex point-to-point control for each chip-resistor pair.
Data Source
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AI summary
The present disclosure provides a single-loop memory device, a double-loop memory device, and a ZQ calibration method. The single-loop memory device includes: a master chip and a plurality of slave chips each provided with a first transmission terminal and a second transmission terminal, where the second transmission terminal of the master chip is connected to the first transmission terminal of the slave chip of a first stage, and the second transmission terminal of the slave chip of each stage is connected to the first transmission terminal of the slave chip of a next stage; and the master chip is provided with a first signal receiver, and the slave chip is provided with a second signal receiver, where the first signal receiver is configured to receive a ZQ calibration command, the master chip starts calibration based on the ZQ calibration command, and the master chip sends a ZQ flag signal after completing the calibration; and the second signal receiver is configured to receive the ZQ flag signal, the slave chip starts the calibration based on the ZQ flag signal, and the slave chip sends the ZQ flag signal after completing the calibration.