LPDDR2 Burst Mode Control Circuit With Fewer Clock Shifters

Solution Overview

Problem

The realization of a burst mode control circuit for LPDDR2 with a burst length of up to 16 is complex and consumes high current due to the need for multiple clock shifters in conventional designs.

Innovation Solution

A burst mode control circuit with a reduced number of clock shifters, featuring a burst period signal generation unit, a burst pulse generation unit, and a column access signal generation unit that generates pulses periodically during the burst operation period, facilitating circuit realization and reducing current consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple clock shifters are used to generate burst pulses for burst length 16, then the burst mode control function is achieved, but the circuit complexity and current consumption increase significantly

Engineering Contradiction:

Improveburst length supportVSAvoidcircuit complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The single clock shifter is designed to perform multiple functions by generating different delay signals (first delay signal for BL8, second delay signal for BL16) that control both the burst pulse generation and the interrupt end signal generation. This multi-functional design eliminates the need for separate clock shifters for different burst lengths, thereby reducing circuit complexity while maintaining adaptability to support both burst length 8 and 16 operations

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines the functions of multiple clock shifters into a single clock shifter that serves all burst length requirements. By merging the clock shifting functionality and using a unified control mechanism with the burst period signal, the circuit achieves the same burst mode control for both BL8 and BL16 without requiring separate dedicated clock shifters, thus simplifying the overall circuit structure

Inventive Principle:

Principle #5Merging (Combining)

2Adaptability or versatility

If multiple clock shifters are used to generate burst pulses for burst length 16, then the burst mode control function is achieved, but the current consumption increases significantly

Engineering Contradiction:

Improveburst length supportVSAvoidcurrent consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The single clock shifter is designed to perform multiple functions by generating different delay signals (first delay signal for BL8, second delay signal for BL16) that control both the burst pulse generation and the interrupt end signal generation. This multi-functional design eliminates the need for separate clock shifters for different burst lengths, thereby reducing circuit complexity while maintaining adaptability to support both burst length 8 and 16 operations

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines the functions of multiple clock shifters into a single clock shifter that serves all burst length requirements. By merging the clock shifting functionality and using a unified control mechanism with the burst period signal, the circuit achieves the same burst mode control for both BL8 and BL16 without requiring separate dedicated clock shifters, thus simplifying the overall circuit structure

Inventive Principle:

Principle #5Merging (Combining)

3Productivity

If conventional burst mode control circuit is used with burst length up to 16, then the data transfer capability is improved, but the realization becomes quite complex

Engineering Contradiction:

Improvedata transfer speedVSAvoidcircuit realization

Core Design Contradiction:

ProductivityVSEase of manufacture

Solution Approach 1:

The single clock shifter is designed to perform multiple functions by generating different delay signals (first delay signal for BL8, second delay signal for BL16) that control both the burst pulse generation and the interrupt end signal generation. This multi-functional design eliminates the need for separate clock shifters for different burst lengths, thereby reducing circuit complexity while maintaining adaptability to support both burst length 8 and 16 operations

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The circuit uses dynamic control signals (burst period signal and interrupt end signal) that change based on the burst length requirement. The single clock shifter dynamically generates appropriate delay signals depending on whether BL8 or BL16 is selected, allowing the circuit to adapt its behavior without requiring separate static configurations for different burst lengths, thus simplifying the realization

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS20100177590A1Burst mode control circuit

Publication Date: 2010.07.15 SK HYNIX INC

AI summary

A burst mode control unit includes a burst period signal generation unit for generating a burst period signal which is enabled during a burst mode operation period, a burst pulse generation unit for generating a burst pulse, which is generated at every predetermined number of cycles during the enabled period of the burst period signal, in response to a read command and a write command, and a column access signal generation unit for receiving the burst signal and a clock signal and generating a column access signal which controls input and output of data during the burst mode operation period.