LPDDR2 Command Decoder Pin Reduction Power Optimization
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Solution Overview
Problem
Existing command decoders in LPDDR2 chips generate unnecessary operations, leading to increased power consumption and inefficient use of command address signals, as they decode signals across multiple edges of a clock pulse signal, resulting in higher power consumption and increased packaging costs due to the need for more input pins.
Innovation Solution
A command decoder configuration that includes an input buffer, a latch circuit, and dedicated command generators that latch and decode command address signals only at specific edges of the clock pulse signal, minimizing unnecessary operations and reducing the number of input pins required by utilizing only the first to fifth command address signals to generate internal commands, thereby reducing power consumption and packaging costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If command decoders decode command address signals across multiple edges of clock pulse signal, then data transmission speed is improved, but power consumption increases due to unnecessary operations
Solution Approach 1:
The command decoder is divided into multiple decoding units, each responsible for decoding at specific clock edges. The first decoding unit decodes at the first edge, the second decoding unit decodes at the second edge, and so on. This segmentation allows the decoder to process commands efficiently at each edge without requiring all units to operate continuously, thereby reducing unnecessary operations and power consumption while maintaining high data transmission speed.
2Adaptability or versatility
If command decoders receive command data and address data through 10 pins, then decoding capability is improved, but packaging cost increases
Solution Approach 1:
The command decoder is designed to receive both command data and address data through a reduced set of pins by utilizing multi-functionality. The same pins are used for different purposes at different clock edges - for example, pins that receive command data at the first edge can receive address data at the second edge. This universal usage of pins reduces the total number of pins required from 10 to fewer, thereby reducing packaging cost while maintaining full decoding capability.
3Speed
If command decoders perform operations at all clock edges, then data transmission speed is improved, but device complexity increases
Solution Approach 1:
The command decoder employs dynamic operation where different decoding units are activated at different clock edges based on the timing requirements. Rather than having all decoding units operate continuously, the system dynamically enables only the necessary units at each edge. This dynamic approach maintains high data transmission speed by ensuring decoding occurs at all edges when needed, while reducing device complexity by avoiding the need for all units to be fully operational simultaneously.
Data Source
AI summary
Command decoders are provided. The command decoder includes an input buffer configured for buffering and receiving command address signals having address information and command information at first, second, third, and fourth edges of a clock pulse signal according to a reference voltage, a latch circuit configured for latching the command address signals output from the input buffer at the first and third edges of the clock pulse signal to generate and output latched signals, a first command generator configured for decoding the latched signals output from the latch circuit at the first edge of the clock pulse signal to generate and output a first internal command, and a second command generator configured for decoding the latched signals output from the latch circuit at the third edge of the clock pulse signal to generate and output a second internal command.