LPDDR4 Memory ECC Retrieval via Command Bit Selection
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Solution Overview
Problem
Low Power Double Data Rate 4 (LPDDR4) memory technology does not natively support error correction codes (ECC), requiring additional communication lines and hardware modifications to read ECC values, which complicates the retrieval of ECC data associated with read operations.
Innovation Solution
The method involves using reserved or unused bits within the LPDDR4 standard commands to select between data and ECC address spaces, allowing ECC values to be retrieved via the same data bus lines (DQ and DQS) without additional communication lines, thereby maintaining compatibility with the LPDDR4 standard and enabling ECC data retrieval without hardware modifications to the memory controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional communication lines are added to read ECC values from memory, then error detection and correction capability is improved, but device complexity and hardware modification requirements increase
Solution Approach 1:
The patent makes the existing data bus lines (DQ and VQ) perform dual functions: transmitting both data and ECC values. By using the same physical infrastructure for multiple purposes, the system achieves error correction capability without adding dedicated ECC bus lines, thus avoiding increased device complexity while maintaining reliability improvement
Solution Approach 2:
The patent merges the data transmission function and ECC transmission function into a single communication channel (the data bus). Instead of having separate paths for data and ECC, the system combines these functions into one unified transmission medium, eliminating the need for additional communication lines and reducing hardware complexity
2Reliability
If dedicated ECC bus lines are used to read ECC values, then error correction reliability is improved, but the number of communication lines and device complexity increase
Solution Approach 1:
The data bus lines are designed to serve multiple purposes: carrying both data signals and ECC signals. This multi-functionality allows the system to maintain reliable error correction capabilities without increasing the quantity of communication lines, as the same physical lines are reused for different signal types at different times
Solution Approach 2:
The patent combines the data communication channel and ECC communication channel into a single shared medium. By merging these functions into existing infrastructure rather than creating separate dedicated lines, the system avoids increasing the total number of communication lines while still achieving reliable error correction
3Reliability
If hardware modifications are made to the memory controller to read ECC values, then error detection capability is improved, but ease of operation and compatibility with LPDDR4 standard decrease
Solution Approach 1:
The memory controller is designed to handle multiple signal types through existing interfaces. The controller can operate in different modes (data mode and ECC mode) using the same physical interface, maintaining compatibility with the LPDDR4 standard while enabling error detection capabilities without requiring hardware modifications
Data Source
AI summary
In an embodiment, a method includes: receiving, via control lines of a parallel interface of a memory device, a first command and a first read command including one or more bits indicative of a first selection that causes a selector circuit to select data from a data memory portion of the memory device; providing, via data lines of the parallel interface, first data from the data memory portion using the selector circuit, where the provided first data is associated with the first read command; receiving, via the control lines, a second command and a second read command including one or more bits indicative of a second selection that causes the selector circuit to select data from an ECC memory portion; and providing, via the data lines, first ECC values from the ECC memory portion using the selector circuit, where the first ECC values are associated with the first data.