LPDDR4 Memory Receiver for Data Strobe Logic Correction

The patent introduces a receiver circuit as an intermediary component between the memory controller and the memory cell array. This receiver circuit includes amplification circuits and logic state adjustment circuits that process the data strobe signals before they reach the memory cells. The intermediary receiver circuit ensures proper signal levels and correct logic states (where inverted data strobe signals have opposite logic states to non-inverted data strobe signals), thereby improving write operation reliability without requiring the memory controller itself to be more complex.

The patent segments the signal processing function into two distinct parts: amplification and logic state adjustment. The receiver circuit includes separate amplification circuits that boost the signal amplitude of data strobe signals, and separate logic state adjustment circuits that ensure the inverted data strobe signals have opposite logic states to the non-inverted data strobe signals. This segmentation allows each circuit to specialize in one function, ensuring both signal strength and logic state correctness are achieved independently and reliably.

The patent implements beforehand cushioning by having the receiver circuit pre-process and correct data strobe signals before they are used in write operations. The logic state adjustment circuits proactively ensure that inverted data strobe signals have the correct opposite logic states relative to non-inverted data strobe signals, anticipating and preventing potential write operation failures. This cushioning approach allows the memory device to maintain strict LPDDR4 standard compatibility while being tolerant of controller signal imperfections, as the receiver circuit compensates for these defects before they can cause harm.