LPDDR5 Chip Select Signal Generation Using Vector Files

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Solution Overview

Problem

The removal of the clock enable signal (CKE) pin in LPDDR5 SDRAM requires alternative methods to implement the clock enable function, necessitating the generation of chip select signals with four different potentials to achieve both power supply control and chip selection operations.

Innovation Solution

A method and apparatus that utilize two vector files to generate chip select signals with four different potentials by sampling external control signals, producing power supply control and chip select control signals, which are then combined to perform power supply control and chip selection operations, leveraging MOS transistors of different types to achieve the required voltage levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the clock enable signal pin is removed in LPDDR5, then the device complexity is reduced, but the ease of operation deteriorates because the clock enable function must be implemented through alternative signal configurations

Engineering Contradiction:
Improvepin countVSAvoidsignal configuration
Core Design Contradiction:
Device complexityVSEase of operation

Solution Approach 1:

The chip select signal is configured to perform dual functions: traditional chip selection and clock enable control. By making the chip select signal universal, the patent eliminates the dedicated CKE pin while maintaining the clock enable function through alternative signal usage, directly resolving the contradiction between reduced pin count and operational complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If chip select signals with four different potentials are generated, then the adaptability is improved to achieve both power supply control and chip selection, but the device complexity increases due to the need for additional signal generation circuitry

Engineering Contradiction:
Improvesignal functionalityVSAvoidsignal generation circuitry
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The signal generation process is segmented into distinct functional blocks: a first vector file generates the power supply control signal, a second vector file generates the chip select control signal, and these are combined to produce the final chip select signal with four different potentials. This segmentation allows complex multi-potential signal generation to be achieved through modular, manageable components

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Two vector files are introduced as intermediary components that facilitate the generation of control signals with different voltage levels. These vector files act as mediators between the input signals and the final multi-potential chip select output, enabling adaptable signal generation without requiring complex direct circuitry

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20240264835A1An Apparatus and Method of Generating Chip Select Signals
Publication Date: 2024.08.08 CHANGXIN MEMORY TECH INC
  • US20240264835A1 patent drawing
  • US20240264835A1 patent drawing
  • US20240264835A1 patent drawing

AI summary

A method and apparatus for generating a chip select signal include: sampling an external control signal to obtain a first and a second sampling signals; inputting the first sampling signal into a first vector file to generate a power supply control signal; inputting the second sampling signal into a second vector file to generate a chip select control signal; generating a chip select signal based on the power supply control signal and the chip select control signal, which include a high potential, a low potential and a high resistance state, the high potential voltages of the power supply control signal and the chip select control signal are different, and the low potential voltages of the power supply control signal and the chip select control signal are different. The disclosure realizes four different potentials for the chip select signals by applying two vector files.