LPDDR5 Memory Clock Phasing to Ease Synchronization Bottlenecks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
LPDDR5 memory systems face challenges in high-speed data processing due to the synchronization of clock signals and duty cycle effects on eye diagrams, which hinder read and write rates.
Innovation Solution
A clock system generating four oscillation signals with specific phase differences, allowing the memory to process high-speed data using low-speed clock signals, eliminating the need for synchronization and duty cycle adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If double-edge sampling mode is used to achieve high-speed data processing, then data transmission rate is improved, but clock signal synchronization complexity and duty cycle adjustment requirements increase
Solution Approach 1:
The patent divides the clock signal system into four independent oscillation signals (CK0, CK90, CK180, CK270) with specific phase differences, where each signal operates independently without requiring synchronization with others. This segmentation eliminates the synchronization complexity inherent in traditional double-edge sampling while maintaining high data transmission rates through phased sampling operations.
2Productivity
If double-edge sampling is implemented to improve data rate, then storage speed is enhanced, but duty cycle stability requirements increase
Solution Approach 1:
By segmenting the sampling operation across four independently generated oscillation signals, each signal maintains its own duty cycle characteristics without affecting others. This eliminates the need for centralized duty cycle stabilization mechanisms while preserving high storage speed performance.
Solution Approach 2:
The patent employs asymmetric phase distribution (0°, 90°, 180°, 270°) among the four oscillation signals, allowing each signal to operate with relaxed duty cycle requirements. The asymmetric phased sampling approach ensures that data can be reliably captured even with varying duty cycles, thereby improving reliability without sacrificing storage speed.
3Reliability
If clock signal synchronization is required for double-edge sampling, then data integrity is maintained, but system complexity and adjustment requirements increase
Solution Approach 1:
The system segments the clocking function into four independent oscillation signal generators, each producing signals with fixed phase relationships. This segmentation eliminates the need for complex synchronization mechanisms while maintaining data integrity through the inherent phase diversity of the segmented signals.
Solution Approach 2:
Each oscillation signal generator is self-contained and autonomously produces its signal without requiring synchronization inputs from other generators. The system achieves coordinated operation through the predetermined phase relationships embedded in the independent signal generation process, eliminating the need for external synchronization control.
Data Source
AI summary
A clock system and a memory are disclosed. The clock system includes a system on chip (SoC) configured to generate a first oscillation signal, a second oscillation signal, a third oscillation signal and a fourth oscillation signal of a same frequency and amplitude. Further, the clock system includes a memory chip configured to output a data signal based on signal edges of the first oscillation signal, the second oscillation signal, the third oscillation signal and the fourth oscillation signal, and output a command/address signal based on the signal edges of the first oscillation signal and the third oscillation signal. The signal edges are rising edges or falling edges.