LPDDR5 Memory Command Embedding Write Data
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Solution Overview
Problem
Early revisions of the JEDEC low power version of DDR5 (LPDDR5) do not provide a Write Pattern mode register to support a full WRITE_X command, limiting power savings to only when writing all 0s, and do not allow programming of any desired data value into an LPDDR5 memory device.
Innovation Solution
Enhancements to the LPDDR5 standard that allow specification of multiple write values by repurposing bits in the CAS command to indicate whether all 0s or all 1s should be written, and using multiplexers to select between internal and external data sources, enabling writing of various data patterns without transferring data over the data bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a Write Pattern mode register is implemented to support full WRITE_X command, then power savings and write versatility are improved, but register space footprint increases
Solution Approach 1:
The patent extracts the write data specification from the data bus and embeds it directly into the command structure. By placing the write data bits in the command bits that would otherwise be unused or less critical, the invention eliminates the need for a dedicated Write Pattern mode register, thus achieving power savings without increasing register space footprint
Solution Approach 2:
The command structure is designed to serve multiple functions: it can specify write data directly in the command bits, support traditional data bus transfers, and enable various write patterns (all 0s, all 1s, or specific patterns). This multi-functionality allows the system to achieve versatility without adding dedicated hardware structures
2Adaptability or versatility
If data is written over the memory data bus, then any desired data value can be written, but bus bandwidth is consumed and power is used
Solution Approach 1:
The invention extracts the write data specification from the data bus and embeds it directly into the command structure. By placing the write data bits in the command bits, the invention eliminates the need to transfer data over the data bus for certain write operations, thus conserving bus bandwidth while maintaining write flexibility
Solution Approach 2:
The command structure itself serves as a copy of the write data specification. Instead of transferring the actual data bits over the bus, the command contains embedded specifications that allow the memory device to generate or select the appropriate write data locally, reducing bus traffic while maintaining data flexibility
Data Source
AI summary
An apparatus is described. The apparatus includes a memory controller having an interface to communicate with a memory. The memory controller comprising logic circuitry to specify one of multiple possible write values to the memory during a write operation with multiple bits of a command that is sent on a command address bus that emanates from the interface. The memory to write any one of the possible write values into its storage cells while the memory interface is in a power saving state wherein the specified one write value is not articulated by the memory controller on a data bus of the interface as part of the write operation.