LPDDR5 Memory Die Interconnects for Individual PHY Training
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Solution Overview
Problem
Current LPDDR5 protocol supports only 16 bits per channel, leading to suboptimal characterization and reduced signal integrity when multiple memory dies are connected in parallel, as they receive the same control signaling, degrading memory device performance.
Innovation Solution
Implementing a 64-bit channel controller with two 32-bit MCs and two 32-bit PHYs, coupled to four LPDDR5 memory dies via a multiplexed manner of chip select (CS) and command-and-address (CA) buses, allowing individual training of each memory die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory dies are connected in parallel to achieve 64-bit channel width, then the channel bandwidth is sufficient, but the signal integrity and characterization quality deteriorates because all dies receive the same control signaling
Solution Approach 1:
The patent divides the single 64-bit channel into multiple independent 16-bit channels, each dedicated to a specific memory die. This segmentation allows each die to have its own dedicated control and data paths, eliminating the interference that occurs when multiple dies share the same channel. The channel controller is also segmented into multiple independent controllers, each managing a specific 16-bit channel and its associated memory die.
Solution Approach 2:
The patent introduces an intermediary layer of channel controllers that sit between the memory controller and the memory dies. Each channel controller independently manages a specific 16-bit channel and can individually train and control its associated memory die. This intermediary structure allows for precise control and characterization of each die's signaling path without interference from other dies.
2Productivity
If four x16 memory dies are used in parallel to achieve 64-bit channel utilization, then the channel capacity is maximized, but the training and characterization process becomes suboptimal because multiple dies are trained together as one combined bus
Solution Approach 1:
The training and characterization process is segmented into independent operations for each memory die. Instead of training all four dies simultaneously on a combined 64-bit bus, each die is trained individually on its dedicated 16-bit channel. This allows for precise measurement and optimization of each die's signaling characteristics without the confounding variables introduced by parallel training of multiple dies.
Solution Approach 2:
The patent applies local quality by providing each memory die with its own dedicated channel controller and 16-bit channel, allowing each die to be trained and characterized with optimal settings specific to its electrical characteristics. This localized approach enables fine-tuned optimization of signal integrity, timing, and voltage levels for each individual die rather than using a one-size-fits-all training approach.
3Device complexity
If a single PHY is used to control multiple memory dies, then the device complexity is reduced, but the ability to individually control and train each memory die is lost
Solution Approach 1:
The PHY layer is segmented into multiple independent PHY instances, with each PHY dedicated to a specific memory die and its 16-bit channel. This segmentation provides the adaptability and individual control needed for optimal memory operation, while each PHY remains a standardized, well-defined component. The segmentation allows each PHY to be independently configured and trained for its specific die without requiring complex cross-die coordination logic.
Data Source
AI summary
This disclosure describes aspects of memory die interconnections to physical layer interfaces (PHYs) that may enable expanded channel bus width and improved signal integrity (SI). In aspects, a memory die is operably coupled to a first PHY via a command-and-address (CA) bus and data input/output (DQ) bus of the first PHY and to a second PHY via a chip select (CS) bus of the second PHY. The second PHY may provide a CS signal to the memory die, and the first PHY can perform a training procedure via CA signaling or DQ signaling. The training procedure may improve SI between the memory die and the PHYs. Additionally, a memory die may be interconnected to different PHYs to expand a channel bus width. Thus, by interconnecting memory dies to one or more PHYs as described herein, improved SI and expanded channel bus width can be achieved.