LPDDR5 Link-ECC Test Device for Noise Interference Validation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In the context of 5G and AI applications, LPDDR5 memory devices face challenges with noise interference during data transmission between controllers and memory devices, necessitating effective error correction mechanisms to ensure robust communication.
Innovation Solution
A test device and method for testing the Link-ECC function, which involves generating error correction codes, dividing data into sections, creating candidate testing data with error bits, and performing multiple testing schemes to write and read data from the device, allowing for the evaluation of error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Link-ECC function is implemented to correct errors in data transmission, then communication reliability is improved, but device complexity increases due to additional error correction code generation and verification mechanisms
Solution Approach 1:
The base data is divided into multiple base data sections, and candidate testing data are generated by selectively combining these sections with different error bit configurations. This segmentation approach allows systematic testing of error correction capabilities without requiring a complete rewrite of the testing mechanism.
Solution Approach 2:
Error bits are predetermined and embedded in candidate testing data before the actual transmission and reception process. This preliminary action enables the system to pre-test error correction functionality under controlled conditions, reducing the complexity of real-time error analysis.
2Measurement precision
If multiple testing schemes are performed to thoroughly validate Link-ECC function, then measurement precision is improved, but loss of time increases due to repeated write and read operations
Solution Approach 1:
The testing process is divided into multiple independent testing schemes, each focusing on specific error correction scenarios. This segmentation allows parallel execution of different test cases and systematic validation of ECC functionality under various error conditions.
Solution Approach 2:
Multiple candidate testing data are continuously written to the tested device without interruption, maintaining a continuous data flow that maximizes the utilization of the communication channel during the testing process.
Data Source
AI summary
A test method includes: generating an error correction code according to a base data; dividing the base data into a plurality of base data sections; generating a plurality of candidate testing data according to the base data, wherein each of the candidate testing data has a plurality of testing data sections, and each of the testing data sections corresponds to each of the base data sections; and, performing a plurality of testing schemes. Each of the testing schemes includes: generating a plurality of write-in test data according to the plurality of candidate testing data, and writing the plurality of write-in test data with the error correction code into a tested device continuously; reading a plurality of mode register values of the tested device and a plurality of readout data from the tested device; and generating a test result according to the plurality of mode register value and the readout data.