Data Processing Circuit Timing Check for LPDDR5 Reliability
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Solution Overview
Problem
The challenge in semiconductor devices adopting LPDDR standards, such as LPDDR5, is ensuring that the data processing circuit correctly processes data signals by accurately checking the timing sequence information to prevent failures during Command Bus Training (CBT) and other regulation checks.
Innovation Solution
A method and apparatus for checking the timing sequence information of data processing circuits by acquiring performance check files of timing sequence logic elements, simulating the circuit, and obtaining timing sequence information, which includes setup and hold times for input ends and latches, to ensure consistent timing and prevent errors during data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If timing sequence information is not accurately checked, then the data processing circuit may fail during Command Bus Training (CBT) and regulation checks, but implementing comprehensive timing checks increases design complexity and testing time
Solution Approach 1:
The patent applies preliminary action by acquiring performance check files and simulating the data processing circuit before actual operation. The timing sequence logic elements are checked in advance during the design phase, allowing timing issues to be identified and corrected before manufacturing, thus ensuring reliability without adding operational complexity
Solution Approach 2:
The patent uses simulation to create a virtual copy of the data processing circuit. By simulating the circuit behavior based on performance check files, the timing sequence can be verified without physically testing every component, reducing the complexity of the checking process while maintaining accuracy
2Manufacturing precision
If comprehensive timing sequence checking is implemented, then the data processing circuit can correctly process data signals, but the checking process requires extensive performance check files and simulation time
Solution Approach 1:
The patent segments the timing sequence checking process into multiple independent timing sequence logic elements. Each element has its own performance check file that can be acquired and simulated separately. This segmentation allows the checking process to be divided into manageable parts, improving timing precision while reducing the overall checking time through parallel processing of different segments
3Measurement precision
If performance check files are acquired for multiple timing sequence logic elements, then accurate timing information can be obtained, but the data processing circuit complexity increases
Solution Approach 1:
The patent implements universality by creating a standardized performance check file format that can be used across multiple timing sequence logic elements. The same simulation framework and checking methodology applies to all timing elements, allowing accurate timing measurement without increasing circuit complexity, as the checking mechanism is universal rather than element-specific
Data Source
AI summary
A method for checking a data processing circuit includes the following. Performance check files of a plurality of timing sequence logic elements in the data processing circuit are acquired, and the data processing circuit is simulated based on the performance check files of the plurality of timing sequence logic elements, so as to obtain timing sequence information of the respective timing sequence logic elements.