Compact Arithmetic Elements Using LPHDR for Parallel Throughput
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Solution Overview
Problem
Conventional computing systems inefficiently utilize transistors, as they are designed for high precision arithmetic, limiting the ability to harness the full computing power of modern silicon-based microprocessors, despite the potential for performing many more operations due to their large number of transistors.
Innovation Solution
The implementation of low precision high dynamic range (LPHDR) processing elements, which perform arithmetic operations with a precision of about 0.1% error, allowing for a greater number of operations per unit time and area, and enabling massively parallel computation on a single chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional high precision arithmetic processing elements are used, then computational accuracy is maintained, but the number of operations per unit time and area is limited
Solution Approach 1:
The patent changes the precision parameter from conventional high precision (e.g., 32-bit or 64-bit floating point) to low precision (e.g., 8-bit or 16-bit integers or floating point). This parameter change allows significantly more arithmetic processing elements to be packed into the same silicon area, enabling massively parallel computation with thousands or millions of operations per cycle, while the accumulated precision error remains acceptable for many computational tasks
Solution Approach 2:
The patent segments the computational task into many independent parallel operations that can be performed simultaneously by numerous low-precision processing elements. By dividing the overall computation into fine-grained independent steps, the system achieves high throughput through massive parallelism, with each segment processed by a dedicated low-precision element
2Productivity
If more arithmetic processing elements are added to increase computing power, then computational throughput improves, but hardware complexity and resource usage increase
Solution Approach 1:
The patent uses numerous inexpensive low-precision arithmetic processing elements that can be densely packed on silicon. Each element is simple and resource-efficient, allowing thousands or millions to be implemented in a single chip. The low cost and small size of each element enable massive parallelism without proportionally increasing overall system complexity
Solution Approach 2:
The patent employs identical or similar low-precision processing elements that can perform multiple arithmetic operations (addition, subtraction, multiplication, division) and be programmed to execute different computational tasks. This universality allows the same hardware architecture to be reused across many operations, reducing overall system complexity compared to having specialized hardware for each function
3Productivity
If low precision arithmetic is used, then more operations can be performed in parallel, but computational accuracy decreases
Solution Approach 1:
The patent performs preliminary error analysis and algorithm design to ensure that low-precision arithmetic produces acceptable results. By pre-planning the computational approach to be tolerant of precision errors (e.g., using algorithms that accumulate error gracefully or require only approximate results), the system achieves high parallel throughput while maintaining sufficient computational reliability for the intended applications
Data Source
AI summary
Low precision computers can be efficient at finding possible answers to search problems. However, sometimes the task demands finding better answers than a single low precision search. A computer system augments low precision computing with a small amount of high precision computing, to improve search quality with little additional computing.