Compact Arithmetic Elements Using LPHDR for Parallel Throughput
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional computing systems waste transistors by using high precision arithmetic operations, limiting the ability to harness the full computing power of silicon-based microprocessors, as they are designed to support precise operations rather than efficient use of transistors for computations.
Innovation Solution
Implementing low precision high dynamic range (LPHDR) processing elements that perform arithmetic operations with a precision of about 0.1% error, allowing for a greater number of operations per unit time and power, and using logarithmic or analog representations to reduce circuit size and increase parallel processing capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high precision arithmetic operations are used, then measurement precision is improved, but device complexity increases and productivity decreases
Solution Approach 1:
The patent changes the precision parameter from traditional high precision (32-bit or 64-bit floating point) to low precision (8-bit or 16-bit fixed point), enabling significantly more arithmetic operations to be performed in parallel while maintaining adequate computational accuracy for many applications
Solution Approach 2:
The patent divides the computing system into many independent, simple arithmetic processing elements that can operate in parallel, rather than using fewer complex high-precision units, thereby increasing overall throughput and computing power delivery
2Measurement precision
If high precision arithmetic operations are used, then measurement precision is improved, but the number of operations per unit time decreases
Solution Approach 1:
The patent changes the precision parameter from traditional high precision (32-bit or 64-bit floating point) to low precision (8-bit or 16-bit fixed point), enabling significantly more arithmetic operations to be performed in parallel while maintaining adequate computational accuracy for many applications
Solution Approach 2:
The patent employs dynamic precision adjustment where the system can adaptively select between different precision levels based on application requirements, allowing high throughput for less demanding tasks while maintaining higher precision when needed
3Reliability
If traditional digital design is used, then reliability is improved, but the number of operations per cycle decreases
Solution Approach 1:
The patent divides the computing system into many independent, simple arithmetic processing elements that can operate in parallel, rather than using fewer complex high-precision units, thereby increasing overall throughput and computing power delivery
Solution Approach 2:
The patent merges multiple simple arithmetic operations into unified processing elements that can be densely packed and operated simultaneously, achieving high parallel throughput while maintaining reliability through redundant simple operations rather than complex sequential logic
Data Source
AI summary
A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range (“LPHDR arithmetic”). Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR arithmetic elements in the processor or other device in certain embodiments of the present invention significantly exceeds (e.g., by at least 20 more than three times) the number of arithmetic elements, if any, in the processor or other device which are designed to perform high dynamic range arithmetic of traditional precision (such as 32 bit or 64 bit floating point arithmetic).