Load Page Table Entry Address Instruction for Virtual Storage Translation

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Solution Overview

Problem

Current dynamic address translation facilities lack enhanced functionality, capability, and protection mechanisms, limiting their effectiveness in managing virtual storage and address translation processes in computer systems.

Innovation Solution

The implementation of a Load Page Table Entry Address (LPTEA) instruction that utilizes a hierarchy of translation tables to translate virtual addresses into real or absolute addresses, with enhanced DAT facilities enabling additional protection and control features such as segment frame absolute addresses and DAT protection fields, allowing for more efficient and secure address management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional dynamic address translation facilities are used, then basic address translation functionality is provided, but enhanced protection mechanisms and control features are lacking

Engineering Contradiction:
Improveprotection mechanismsVSAvoidfunctionality
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The address translation process is segmented into multiple hierarchical levels (segment tables and page tables). Segment table entries contain format control fields that determine whether to use large block addressing or traditional page table translation, enabling differentiated protection mechanisms at each level of the hierarchy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically adapts its translation approach based on the format control field in segment table entries. When the format control field indicates large block mode, the system uses segment frame absolute addresses for direct translation; otherwise, it proceeds with traditional page table translation, providing flexible and adaptive address translation.

Inventive Principle:
Principle #15Dynamics

2Productivity

If enhanced DAT facility with format control field is enabled, then large blocks of data can be addressed directly, but compatibility with traditional translation methods is reduced

Engineering Contradiction:
Improveaddress translation efficiencyVSAvoidtranslation method compatibility
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

Different segments of the address space can have different translation characteristics. The format control field in each segment table entry allows individual segments to be configured for either large block direct addressing or traditional page table translation, enabling local optimization without affecting the entire address space.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The segment table entry structure is designed to support multiple translation modes universally. The format control field acts as a switch that enables the same hardware facility to perform both large block direct addressing and traditional page table translation, making the system multi-functional and compatible with different addressing requirements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Length of moving object

If segment frame absolute addresses are used, then direct addressing of large data blocks is achieved, but fine-grained control over smaller data blocks is lost

Engineering Contradiction:
Improvedata block sizeVSAvoidgranularity control
Core Design Contradiction:
Length of moving objectVSEase of operation

Solution Approach 1:

The system dynamically selects the appropriate translation granularity based on the format control field. For large data blocks, segment frame absolute addresses provide direct access; for smaller data blocks requiring fine-grained control, the system automatically falls back to page table translation, maintaining operational flexibility across different data sizes.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8930673B2Load page table entry address instruction execution based on an address translation format control field
Publication Date: 2015.01.06 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US8930673B2 patent drawing
  • US8930673B2 patent drawing
  • US8930673B2 patent drawing

AI summary

What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode indicating that a load page table entry address function is to be performed. The machine instruction contains an M field, a first field identifying a first general register, and a second field identifying a second general register. Based on the contents of the M field, an initial origin address of a hierarchy of address translation tables having at least one segment table is obtained. Based on the obtained initial origin address, dynamic address translation is performed until a page table entry is obtained. The page table entry address is saved in the identified first general register.