LPXPIPE MAC PHY Interface Pin Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The limited number of pins in PCI Express applications constrains the interconnection between MAC and PHY chips, particularly due to increased signal frequencies and routing space constraints, making it challenging to implement integrated devices with efficient communication approaches.
Innovation Solution
A low pin count PCI Express PHY interface (LPXPIPE) is implemented, using an internal data bus to transmit a subset of symbols between the MAC and PHY, with command information encoded into unused symbols, reducing the pin count while maintaining data transmission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of pins is increased to accommodate more signal lines between MAC and PHY chips, then the routing flexibility and signal transmission capability are improved, but the chip package size and manufacturing complexity increase
Solution Approach 1:
The patent combines multiple separate signal lines (data lines and command/status lines) into a single shared data bus. The command/status lines are multiplexed with data lines, allowing the same physical pins to carry different types of signals at different times. This merging reduces the total pin count from what would be required for separate dedicated lines while maintaining full functionality.
Solution Approach 2:
The patent implements dynamic signal multiplexing where the data bus can switch between carrying data signals and command/status signals based on operational mode. The system dynamically allocates the shared bus resources - during data transmission phases, the bus carries data; during control phases, the same bus carries command and status information. This dynamic usage maximizes the utility of limited pins.
2Reliability
If dedicated command and status lines are added between MAC and PHY chips, then the control signal transmission is improved, but the pin count increases
Solution Approach 1:
The patent merges command lines, status lines, and data lines into a single shared data bus structure. Instead of having separate physical lines for commands, status, and data, the system uses one bus that can be configured to carry any of these signal types. This consolidation dramatically reduces the pin count while ensuring reliable control signal transmission through proper protocol management.
Solution Approach 2:
The shared data bus is designed to be universal, serving multiple functions: it can transmit data bidirectionally, carry command signals from MAC to PHY, and return status signals from PHY to MAC. This multi-functional design eliminates the need for dedicated lines for each signal type, reducing the overall pin count while maintaining reliable control transmission.
3Productivity
If the signal frequency is increased to improve data transmission speed, then the productivity is improved, but the routing space requirements and signal integrity constraints increase
Solution Approach 1:
The patent combines command/status transmissions with data transmission on the same bus infrastructure. By multiplexing control signals onto the data bus, the system eliminates the need for additional dedicated control signal lines that would be required at high frequencies. This reduces the overall routing complexity and space requirements while maintaining high data transmission speeds on the shared bus.
Data Source
AI summary
According to an example embodiment of the present invention, a method is implemented for transmitting data between a Media Access Control Layer (MAC) (100) and a Physical Layer (PHY) (150) using an internal data bus for transmitting a set of internal symbols between the MAC (100) and PHY (150). A subset of internal symbols does not have a corresponding PHY symbol. An external data bus carries data symbols. An external interface (102, 118) provides command information on one or more dedicated command lines and provides the data symbols. An encoder (108, 110) encodes the provided command information into one or more of the subset of internal symbols. An internal interface (106, 107, 109, 111) transmits the one or more of the subset of internal symbols and the data symbols between the MAC (100) and PHY (150) using the internal data bus.