Low Dynamic Resistance Low Capacitance Diode Design
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Solution Overview
Problem
Existing semiconductor diodes face challenges in simultaneously minimizing dynamic resistance and capacitance while maintaining a desired breakdown voltage, as increasing dopant density in the substrate to improve dynamic resistance reduces the breakdown voltage.
Innovation Solution
A semiconductor device design featuring an n-type substrate with a lightly-doped n-type layer and a p-type layer, including a p-type buried layer with a high peak dopant density extending through the n-type layer to the substrate, and an n-type region in the p-type layer, which allows for the adjustment of breakdown voltage and capacitance through dopant density and layer thickness optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the dopant density in the substrate is increased to improve dynamic resistance, then the dynamic resistance decreases, but the breakdown voltage reduces
Solution Approach 1:
The diode structure is divided into multiple distinct layers with different doping concentrations: a lightly-doped drift layer for voltage support, a heavily-doped buried layer for low dynamic resistance, and a moderate-doped contact layer. This segmentation allows each layer to optimize for its specific function without compromising the other parameters.
Solution Approach 2:
Different regions of the diode are assigned different dopant densities tailored to their specific functional requirements. The drift layer maintains low doping to sustain high breakdown voltage, while the buried layer uses high doping to minimize dynamic resistance, and the contact layer uses moderate doping for optimal electrical contact.
Data Source
AI summary
A low dynamic resistance, low capacitance diode of a semiconductor device includes a heavily-doped n-type substrate. A lightly-doped n-type layer 1 micron to 5 microns thick is disposed on the n-type substrate. A lightly-doped p-type layer 3 microns to 8 microns thick is disposed on the n-type layer. The low dynamic resistance, low capacitance diode, of the semiconductor device includes a p-type buried layer, with a peak dopant density above 1×1017 cm−3, extending from the p-type layer through the n-type layer to the n-type substrate. The low dynamic resistance, low capacitance diode also includes an n-type region disposed in the p-type layer, extending to a top surface of the p-type layer.